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DM3725 Datasheet(PDF) 181 Page - Texas Instruments

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Part # DM3725
Description  Applications Processor
PDF  268 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DM3725 Datasheet(HTML) 181 Page - Texas Instruments

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DM3730, DM3725
www.ti.com
SPRS685 – AUGUST 2010
6.4.2.1.3 PCB Stackup
The minimum stackup required for routing the DM37x is a six layer stack as shown in Table 6-14.
Additional layers may be added to the PCB stack up to accommodate other circuitry or to reduce the size
of the PCB footprint.
Table 6-14. DM37x Minimum PCB Stack Up
LAYER
TYPE
DESCRIPTION
1
Signal
Top Routing Mostly Horizontal
2
Plane
Ground
3
Plane
Power
4
Signal
Internal Routing
5
Plane
Ground
6
Signal
Bottom Routing Mostly Vertical
Table 6-15. PCB Stack Up Specifications
NO.
PARAMETER
MIN
TYP
MAX
UNIT
NOTES
1
PCB Routing/Plane Layers
6
2
Signal Routing Layers
3
3
Full ground layers under LPDDR routing region
2
4
Number of ground plane cuts allowed within LPDDR routing region
0
Number of ground reference planes required for each LPDDR routing 1
5
1
layer
Number of layers between LPDDR routing layer and reference ground 0
6
0
plane
7
PCB Routing Feature Size
4
Mils
8
PCB Trace Width w
4
Mils
9
PCB BGA escape via pad size
18
Mils
10
PCB BGA escape via hole size
8
Mils
11
Device BGA Pad Size
See Note(1)
12
LPDDR Device BGA Pad Size
See Note(2)
13
Single Ended Impedance, ZO
50
75
Ω
14
Impedance Control
Z-5
Z
Z + 5
Ω
See Note(3)
(1)
Please see the Flip Chip Ball Grid Array Package Reference Guide (literature number SPRU811) for device BGA pad size.
(2)
Please see the LPDDR device manufacturer documentation for the LPDDR device BGA pad size.
(3)
Z is the nominal singled ended impedance selected for the PCB specified by item 12.
Copyright © 2010, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics
181
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Product Folder Link(s): DM3730 DM3725



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