DM3725 datasheet(186/268 Pages) TI

186 / 268 page

DM3730, DM3725

SPRS685 – AUGUST 2010

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Table 6-20. CPI Timing Requirements—12-Bit SYNC Normal Progressive Mode(4) (5)

NO.

PARAMETER

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

ISP17

1 / tc(pclk)

Frequency(1), input pixel clock cam_pclk

MHz

ISP18

tw(pclkH)

Typical pulse duration, input pixel clock cam_pclk high

0.5P(2)

ISP18

tw(pclkL)

Typical pulse duration, input pixel clock cam_pclk low

0.5P(2)

tdc(pclk)

Duty cycle error, input pixel clock cam_pclk

0.5P(2) -

3.465

6.93

tJ(pclk)

Cycle jitter(3), input pixel clock cam_pclk

0.0649*P

(2)

ISP19

tsu(dV-pclkH)

Setup time, input data cam_d[11:0] valid before input

1.82

3.25

pixel clock cam_pclk rising edge

ISP20

th(pclkH-dV)

Hold time, input data cam_d[11:0] valid after input

1.82

3.25

pixel clock cam_pclk rising edge

ISP21

tsu(dV-vsH)

Setup time, input vertical synchronization cam_vs valid

1.82

3.25

before input pixel clock cam_pclk rising edge

ISP22

th(pclkH-vsV)

Hold time, input vertical synchronization cam_vs valid

1.82

3.25

after input pixel clock cam_pclk rising edge

ISP23

tsu(dV-hsH)

Setup time, input horizontal synchronization cam_hs

1.82

3.25

valid before input pixel clock cam_pclk rising edge

ISP24

th(pclkH-hsV)

Hold time, input horizontal synchronization cam_hs

1.82

3.25

valid after input pixel clock cam_pclk rising edge

ISP25

tsu(dV-hsH)

Setup time, input write enable cam_wen valid before

1.82

3.25

input pixel clock cam_pclk rising edge

ISP26

th(pclkH-hsV)

Hold time, input write enable cam_wen valid after input

1.82

3.25

pixel clock cam_pclk rising edge

(1) Related with the input maximum frequency supported by the ISP module.

(2) P = cam_pclk period in ns

(3) Maximum cycle jitter supported by cam_pclk input clock.

(4) The timing requirements are assured up to the cycle jitter and duty cycle error conditions specified.

(5) See Section 4.3.4, Processor Clocks.

186

Timing Requirements and Switching Characteristics

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