DM3725 datasheet(201/268 Pages) TI

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SPRS685 – AUGUST 2010

6.5.2.2.2 DSS—Parallel Interface—RFBI Mode—Pico DLP

The Remote Frame Buffer Interface (RFBI) module can provide also the necessary control signals and

data to interface to the Pico DLP driver of the Pico DLP panel. Table 6-36 assumes testing over the

recommended operating conditions and electrical characteristic conditions below (see Figure 6-31).

Table 6-36. DSS Timing Conditions—RFBI Mode—Pico DLP

TIMING CONDITION PARAMETER

VALUE

UNIT

MIN

MAX

Output Condition

CLOAD

Output load capacitance(1)

(1) Buffer strength configuration: LB0 = 0

To use Pico DLP application, RFBI register must be configured as shown in Table 6-37:

Table 6-37. DSS Register Configuration—RFBI Mode—Pico DLP

DESCRIPTION

BIT

VALUES

Selection parallel mode

RFBI_CONFIGi and

[1:0]

0b11: 16-bit parallel output interface

ParallelMode

selected

Time Granularity (multiplies signal timing

RFBI_CONFIGi

[4]

0b0: x2 latency disable

latencies by 2).

andTimeGranularity

CS signal assertion time from Start Access

RFBI_ONOFF_TIMEi and

[3:0]

0b0000

Time

CSOnTime

CS signal de-assertion time from Start Access

RFBI_ONOFF_TIMEi and

[9:4]

0b000100: 4 cycles

Time

CSOffTime

WE signal assertion time from Start Access

RFBI_ONOFF_TIMEi and

[13:10]

0b0000

Time

WEOnTime

WE signal de-assertion time from Start Access

RFBI_ONOFF_TIMEi and

[19:14]

0b000010: 2 cycles

Time

WEOffTime

RE signal assertion time from Start Access

RFBI_ONOFF_TIMEi and

[23:20]

0b0000

Time

REOnTime

RE signal de-assertion time from Start Access

RFBI_ONOFF_TIMEi and

[29:24]

0b0000

Time

REOffTime

Write cycle time

RFBI_CYCLE_TIMEi and

[5:0]

0b000100: 4 cycles

WECycleTime

Read cycle time

RFBI_CYCLE_TIMEi and

[11:6]

0b000000

ReCycleTime

CS pulse width

RFBI_CYCLE_TIMEi and

[17:12]

0b000000

CSPulseWidth

Read to Write CS pulse width enable

RFBI_CYCLE_TIMEi and

[18]

0b0

RWEnable

Read to Read CS pulse width enable

RFBI_CYCLE_TIMEi and

[19]

0b0

RREnable

Write to Write CS pulse width enable

RFBI_CYCLE_TIMEi and

[20]

0b0

WWEnable

Write to Read CS pulse width enable

RFBI_CYCLE_TIMEi and

[21]

0b0

WREnable

From Start Access Time to CLK rising edge

RFBI_CYCLE_TIMEi and

[27:22]

0b000000

used for the first data capture

AccessTime

(1) i is equal to 0 or 1. For more information, see the DSS chapter in the AM/DM37x Multimedia Device Technical Reference Manual

(literature number SPRUGN4).

Timing Requirements and Switching Characteristics

201

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