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DM3725 Datasheet(PDF) 218 Page - Texas Instruments |
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DM3725 Datasheet(HTML) 218 Page - Texas Instruments |
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218 / 268 page  DM3730, DM3725 SPRS685 – AUGUST 2010 www.ti.com 6.6.2.2 McSPI—Master Mode In master mode, McSPI supports multichannel communication. McSPI initiates a data transfer on the data lines (SPIDAT [1:0]) and generates clock (SPICLK) and control signals (SPIEN) to a single SPI slave device at a time. Table 6-72 and Table 6-75 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 6-42 and Figure 6-43). Table 6-71. McSPI Timing Conditions—Master Mode(1) TIMING CONDITION PARAMETER VALUE UNIT MIN MAX Input Conditions tR Input signal rise time 4 ns tF Input signal fall time 4 ns Output Conditions McSPI1, McSPI2, McSPI3, and McSPI4 CLOAD Output load capacitance for spix_csn signals 20 pF McSPI2 and McSPI3 CLOAD Output load capacitance for spix_clk and spix_simo 30 pF McSPI1 and McSPI4 CLOAD Output load capacitance for spix_clk and spix_simo 20 pF (1) Buffer strength configuration: LB0 = 1. Table 6-72. McSPI1, 2, and 4 Timing Requirements—Master Mode(1) (2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX SM2 tsu(SOMIV-CLKAE) Setup time, mcspix_somi valid before mcspix_clk 1.1 1.5 ns active edge SM3 th(SOMIV-CLKAE) Hold time, mcspix_somi valid after mcspix_clk active 1.9 2.8 ns edge (1) In mcspix, x is equal to 1, 2, or 4. In mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 4. (2) See Section 4.3.4, Processor Clocks. Table 6-73. McSPI1, 2, and 4 Switching Characteristics—Master Mode(1) (6) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX SM0 1/tc(CLK) Frequency, mcspix_clk 48 24 MHz SM1 tw(CLK) Pulse duration, mcspix_clk high or low 0.45*P(3) 0.55*P(3) 0.45*P(3) 0.55*P(3) ns tR(clk) Rise time, output clock mcspi1_clk and mcspi4_clk 5.72 5.68 ns Rise time, output clock mcspi2_clk 7.33 7.31 tF(clk) Fall time, output clock mcspi1_clk and mcspi4_clk 5.22 5.21 ns Fall time, output clock mcspi2_clk 6.77 6.71 SM4 td(CLKAE-SIMOV) Delay time, mcspix_clk active edge to mcspix_simo –2.1 5.0 –2.1 11.3 ns shifted SM5 td(CSnA-CLKFE) Delay time, mcspix_csi active to Modes 1 and 3(2) A(4) – 3.2 A(4) – 4.4 ns mcspix_clk first edge Modes 0 and 2(2) B(5) – 3.2 B(5) – 4.4 ns SM6 td(CLKLE-CSnI) Delay time, mcspix_clk last Modes 1 and 3(2) B(5) – 3.2 B(5) – 4.4 ns edge to mcspix_csi inactive Modes 0 and 2(2) A(4) – 3.2 A(4) – 4.4 ns SM7 td(CSnAE-SIMOV) Delay time, mcspix_csi active edge to mcspix_simo 5.0 11.3 ns shifted 218 Timing Requirements and Switching Characteristics Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): DM3730 DM3725 |
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