ADS1178IPAPR datasheet(25/39 Pages) TI1

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APPLICATION INFORMATION

ADS1174

ADS1178

www.ti.com ........................................................................................................................................ SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008

5. Reference Inputs: It is recommended to use

obtain

the

specified

performance

from

the

either a minimum 10

µF tantalum with a 0.1µF

ADS1174/78, the following layout and component

ceramic capacitor, or a single 1

µF ceramic

guidelines should be considered.

capacitor, directly across the reference inputs,

1. Power Supplies: The device requires three

VREFP and VREFN. The reference input should

power supplies for operation: DVDD, IOVDD, and

be driven by a low-impedance source. For best

AVDD. The range for DVDD is 1.65V to 1.95V;

performance, the reference should be low-noise.

the range of IOVDD is 1.65V to 3.6V; and AVDD

6. Analog Inputs: The analog input pins must be

is restricted to 4.75V to 5.25V. For all supplies,

driven

differentially

achieve

specified

use a 10

µF tantalum capacitor, bypassed with a

performance.

true

differential

driver

0.1

µF ceramic capacitor, placed close to the

transformer (for ac applications) can be used for

device pins. Alternatively, a single 10

µF ceramic

this purpose. Route the analog inputs tracks

capacitor can be used. The supplies should be

(AINP, AINN) as a pair from the buffer to the

relatively free of noise and should not be shared

converter using short, direct tracks and away

with devices that produce voltage spikes (such as

from digital tracks.

relays, LED display drivers, etc.). If a switching

power-supply source is used, the voltage ripple

A 1nF to 10nF capacitor should be used directly

should be low (< 2mV) and the switching

across the analog input pins, AINP and AINN. A

frequency outside the passband of the converter.

low-k dielectric (such as COG or film type) should

be used to maintain low THD. Capacitors from

2. Ground Plane: A single ground plane connecting

each analog input to ground can be used. They

both AGND and DGND pins can be used. If

should be no larger than 1/10 the size of the

separate digital and analog grounds are used,

difference capacitor (typically 100pF) to preserve

connect the grounds together at the converter, or

the AC common-mode performance.

at the power entry point of the printed circuit

board (PCB).

7. Component Placement: Place the power supply,

analog

input,

and

reference

input

bypass

3. Digital

Inputs:

recommended

capacitors as close as possible to the device

source-terminate the digital inputs to the device

pins. This layout is particularly important for the

with 50

Ω series resistors. The resistors should be

small-value ceramic capacitors. Surface-mount

placed close to the driving end of the digital

components are recommended to avoid the

source (oscillator, logic gates, DSP, etc.) This

higher inductance of leaded components.

placement helps to reduce ringing on the digital

lines,

which

may

lead

degraded

ADC

performance.

Figure 26 to Figure 28 illustrate basic connections

4. Analog/Digital Circuits: Place analog circuitry

and

interfaces

that

can

used

with

the

(input buffer, reference) and associated tracks

ADS1174/78.

together, keeping them away from digital circuitry

(DSP,

microcontroller,

logic).

Avoid

crossing

digital tracks across analog tracks to reduce

noise coupling and crosstalk.

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