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ADS1178IPAPR Datasheet(PDF) 12 Page - Texas Instruments |
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ADS1178IPAPR Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 39 page ![]() ESDProtection AVDD AGND AVDD AINP 9pF AINN AGND S 1 S 1 S 2 ON OFF S 1 ON OFF S 2 t SAMPLE MOD =1/f AINP AINN Z =14k eff MO W ´ (6.75MHz/f D) ADS1174 ADS1178 SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 ........................................................................................................................................ www.ti.com While the ADS1174/78 measures the differential input signal, the absolute input voltage is also important. This is the voltage on either input (AINP or AINN) with respect to AGND. The range for this voltage is: –0.1V < (AINN or AINP) < AVDD + 0.1V If either input is taken below –0.4V or above (AVDD + 0.4), ESD protection diodes on the inputs may turn on. If these conditions are possible, external Schottky clamp diodes or series resistors may be required to limit the input current to safe levels (see Absolute Maximum Ratings table). The ADS1174/78 is a high-performance ADC. For optimum performance, it is critical that the appropriate circuitry be used to drive the ADS1174/78 inputs. See Figure 7. Equivalent Analog Input Circuitry the Applications Information section for the recommended circuits. The ADS1174/78 uses switched-capacitor circuitry to measure the input voltage. Internal capacitors are charged by the inputs and then discharged. Figure 7 shows a conceptual diagram of these circuits. Switch S2 represents the net effect of the modulator circuitry in discharging the sampling capacitor; the actual Figure 8. S1 and S2 Switch Timing for Figure 7 implementation is different. The timing for switches S1 and S2 is shown in Figure 8. The sampling time (tSAMPLE) is the inverse of modulator sampling Table 3. Modulator Frequency (fMOD) versus Mode frequency (fMOD) and is a function of the mode, the Selection CLKDIV input, and frequency of CLK, as shown in MODE SELECTION CLKDIV fMOD Table 3. 1 fCLK/8 The average load presented by the switched High-Speed 0 fCLK/4 capacitor input can be modeled with an effective differential impedance, as shown in Figure 9. Note 1 fCLK/40 Low-Power that the effective impedance is a function of fMOD. 0 fCLK/8 Figure 9. Effective Input Impedances 12 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ADS1174 ADS1178 |
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