ADS1178IPAPR datasheet(10/39 Pages) TI1

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FUNCTIONAL DESCRIPTION

FREQUENCY RESPONSE

-20

-40

-60

-80

-100

-120

-140

0.4

NormalizedInputFrequency(f

IN/fDATA)

0.2

0.6

0.8

1.0

SAMPLING APERTURE MATCHING

0.02

-0.02

-0.04

-0.06

-0.08

-0.10

0.2

NormalizedInputFrequency(f /f

IN DATA)

0.1

0.3

0.4

0.5

0.6

ADS1174

ADS1178

SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008 ........................................................................................................................................ www.ti.com

The ADS1174 and ADS1178 are 16-bit delta/sigma

The digital filter sets the overall frequency response.

ADCs consisting of independent converters that

The filter uses a multi-stage FIR topology to provide

digitize input signals simultaneously. The ADS1174

linear phase with minimal passband ripple and high

consists of four independent converters, while the

stop band attenuation. The oversampling ratio of the

ADS1178 has eight independent converters.

digital filter (that is, the ratio of the modulator

sampling to the output data rate: fMOD/fDATA) is 64 for

The converter is composed of two main functional

both High-Speed and Low-Power modes.

blocks

perform

the

ADC

conversions:

the

modulator and the digital filter.

The

modulator

Figure 2 shows the frequency response of the

samples the input signal together with sampling the

ADS1174/78 normalized to fDATA. Figure 3 shows the

reference voltage to produce a 1's density output

passband ripple. The transition from passband to stop

stream.

The

density

the

output

stream

band is illustrated in Figure 4. The overall frequency

proportional to the analog input level relative to the

response repeats at 64x multiples of the modulator

reference voltage. The pulse stream is filtered by the

frequency fMOD, as shown in Figure 5.

internal digital filter where the output conversion

result is produced.

In operation, the signal inputs and reference inputs

are sampled by the modulator at a high rate (typically

64x higher than the final output data rate). The

quantization noise of the modulator is moved to a

higher frequency range where the internal digital filter

removes it. This process results in very low levels of

noise within the signal passband.

Because the input signal is sampled at a very high

rate, input signal aliasing does not occur until the

input signal frequency approaches the modulator

sampling rate. The high sampling rate of the

modulator greatly relaxes the requirement of external

antialiasing filters, thus eliminating passband phase

errors that otherwise may be caused by the analog

Figure 2. Frequency Response

filter.

The converters of the ADS1174/78 operate from the

same CLK input. The CLK input controls the timing of

the modulator sampling instant. The converter is

designed so that the sampling skew (or modulator

sampling

aperture

match)

between

channels

controlled.

Furthermore,

the

digital

filters

are

synchronized to start the convolution phase at the

same modulator clock cycle. This design results in

excellent phase match among the ADS1174/78

channels.

The phase match of one four-channel ADS1174 to

that of another ADS1174 may not have the same

degree of sampling match (the same is true for two

8-channel ADS1178s). As a result of manufacturing

variations, differences in internal propagation delay of

Figure 3. Passband Response

the internal CLK signal coupled with differences of

the arrival of the external CLK signal to each device

may cause larger sampling match errors. Equal

length CLK traces or external clock distribution

devices can be used to control the arrival of the CLK

signals to help reduce the sampling match error.

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ADS1178IPAPR Datasheet(PDF) 10 Page - Texas Instruments

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