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TLE7269G Datasheet(PDF) 29 Page - Infineon Technologies AG |
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TLE7269G Datasheet(HTML) 29 Page - Infineon Technologies AG |
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29 / 34 page ![]() Data Sheet 29 Rev. 1.2, 2007-11-13 TLE7269G Application Information 7.3 Master Termination To achieve the required timings for the dominant to recessive transition of the bus signal an additional external termination resistor of 1 k Ω is mandatory. It is recommended to place this resistor at the master node. To avoid reverse currents from the bus line into the battery supply line it is recommended to place a diode in series with the external pull-up. For small systems (low bus capacitance) the EMC performance of the system is supported by an additional capacitor of at least 1 nF at the master node (see Figure 17 and Figure 18).The values for the Master Termination resistor and the bus capacitance influence the performance of the LIN network. They depend on the number of nodes inside the LIN network and on the parasitic cable capacitances of the LIN bus wiring. 7.4 External Capacitors A capacitor of 10 µF at the supply voltage input V S buffers the input voltage. In combination with the required reverse polarity diode this prevents the device from detecting a power down conditions in case of negative transients on the supply line (see Figure 17 and Figure 18). The 100 nF capacitor close to the V S pin and a 33 nF capacitor close to the VIO pin of the TLE7269G are required to get the best EMC performance. |
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