34704 datasheet(28/54 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

34704

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

POWER-UP SEQUENCE

Following is the power up sequence from a battery

connection or a Power On signal through the ONOFF pin.

1. Battery initially connected to VIN.

2. LION pin is used to determine if a battery is being used

(High for Li-Ion battery).

3. At initial power up from a cold start like the above with

the battery first connected, the status of the ONOFF

pin is ignored and 34704 moves forward to step (5).

4. After the cold start or battery insertion power up,

activity on the ONOFF pin is used to determine if the

device is enabled or disabled. If the device is disabled,

then nothing happens. If the device is enabled then,

34704 moves forward to step (5).

5. The input battery UVLO signal de-asserts if the input

voltage is above the UVLO rising threshold.

6. REG1 VG starts up in peak detect PFM and REG1 VG

output starts rising.

7. VDDI output voltage will start tracking REG1 VG output.

8. When REG1 VG output rises high enough such that

VDDI voltage is in regulation a POR signal is released

and all internal circuitry can be enabled. I2C

communication will remain disabled for normal power

up sequence. The values of the FREQ and SS pins are

read at this point.

9. REG1 PWM control loop can take over control of

REG1 output once the VG voltage reaches a certain

threshold set internally.

10. When REG1 is in regulation, it will be used to supply

the Power MOSFET gate voltage for all of the other

regulators except REG7.

11. REG3 is enabled, then when REG3 is in regulation.

12. REG2 is enabled, then when REG2 is in regulation.

13. REG4 is enabled, then when REG4 is in regulation.

14. I2C communication is enabled now since the processor

supplies are up.

15. 34704 will de-assert the RST signal to indicate a

“Power Good” after 10 ms of wait time. This output will

be connected to the reset pin of the microprocessor.

16. The microprocessor then takes over and can enable

REG1 VOUT1 and REG5 through REG8. The

processor needs to send a command for REG8 mode

of operation. The processor can also change REG5-8

soft start time before enabling them. The processor can

also power down the system with an ALLOFF

command.

For power sequencing needs, the different regulators are

grouped based on their function and how they relate to each

other and the entire system. This makes power sequencing

control a much easier task for the user where most of the

group internal sequencing in now handled by the PMIC. All

the processor has to do is to command the group and not

each regulator.

The regulators groups are as follows:

• GrpA: Includes REG1 (VOUT1)

• GrpB: Includes REG2, REG3, and REG4

• GrpC: Includes REG5, REG6, and REG7

• GrpD: Includes REG8

• GrpE: This is a special group. It includes REG5 when

GrpC/E power sequencing option#1 is chosen

SHUTDOWN SEQUENCES

• Processor can disable VOUT1 (GrpA) at any point it

desires

• Processor can disable REG8 (GrpD) at any point it desires

• Processor can disable REG5 (GrpE) at any point it desires

if sequencing option#1 is picked

• Processor can shutdown GrpC according to the power

sequencing options 1, 2, 3, or 4 (see section “I2C User

Interface”)

• If any regulator in GrpC is shutting down due to a fault, the

other regulators in GrpC will also shutdown by following

the GrpC power sequencing options 1, 2, 3, or 4 (see

section “I2C User Interface”)

• If any regulator in GrpB is shutting down due to a fault, the

other regulators in GrpB will also shutdown by following

the processor supplies shutdown sequence. Then, GrpA,

GrpC, GrpD, and GrpE (if applicable) will simultaneously

shutdown keeping any sequencing within each group as

necessary. VG will stay alive to perform a power up retry

for GrpB but only for one time. If the power up cycle is

successful, then normal operation is back. If the fault

returns, then the shutdown sequence is repeated and then

VG shuts down

• Processor can shutdown the 34704 by sending an

“ALLOFF” command, then GrpA, GrpC, GrpD, and GrpE

(if applicable) will simultaneously shutdown keeping any

sequencing within each group as necessary. Then, GrpB

will shutdown according to the processor supply shutdown

sequence. Then, VG will shut down.

• The previous shutdown event can also happen through the

ONOFF pin by pressing and holding the pin for a time

period (programmable through I2C with a default of 1sec)

• During battery depletion and when the input voltage

passes the UVLO falling threshold, all of the outputs will be

disabled without honouring the power down sequence

This is to guarantee that the outputs are off and battery is

not depleted further.

34704 Datasheet(PDF) 28 Page - Freescale Semiconductor, Inc

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