TPS51916

SLUSAE1D – DECEMBER 2010 – REVISED JUNE 2012

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output capacitor(s), VTTGND, GND and PGND pins should be connected to system GND plane near the

device as shown in Figure 41.

•

Because the TPS51916 controls output voltage referring to voltage across VOUT capacitor, VDDQSNS

should be connected to the positive node of VOUT capacitor using different trace from that for VLDOIN.

Remember that this sensing potential is the reference voltage of VTTREF. Avoid any noise generative lines.

GND pin refers to the negative node of VOUT capacitor.

•

Connect the overcurrent setting resistor from TRIP pin to GND pin and make the connections as close as

possible to the device to avoid coupling from a high-voltage switching node.

•

Connect the frequency and mode setting resistor from MODE pin to GND pin ground, and make the

connections as close as possible to the device to avoid coupling from a high-voltage switching node.

•

Connections from gate drivers to the respective gate of the high-side or the low-side MOSFET should be as

short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace and via(s) of at least 0.5

mm (20 mils) diameter along this trace.

•

The PCB trace defined as SW node, which connects to the source of the high-side MOSFET, the drain of the

low-side MOSFET and the high-voltage side of the inductor, should be as short and wide as possible.

•

VLDOIN should be connected to VOUT with short and wide traces. An input bypass capacitor should be

placed as close as possible to the pin with short and wide connections. The negative node of the capacitor

should be connected to system GND plane.

•

The output capacitor for VTT should be placed close to the pins with a short and wide connection in order to

avoid additional ESR and/or ESL of the trace.

•

VTTSNS should be connected to the positive node of the VTT output capacitor(s) using a separate trace from

the high-current power line. When remote sensing is required attach the output capacitor(s) at that point.

Also, it is recommended to minimize any additional ESR and/or ESL of ground trace between GND pin and

the output capacitor(s).

•

Consider adding a low pass filter (LPF) at VTTSNS in case the ESR of the VTT output capacitor(s) is larger

than 2 m

Ω.

•

In order to effectively remove heat from the package, prepare a thermal land and solder to the package

thermal pad. Wide trace of the component-side copper, connected to this thermal land, helps heat spreading.

Numerous vias with a 0.3-mm diameter connected from the thermal land to the internal/solder-side ground

plane(s) should be used to help dissipation. The thermal land can be connected to either AGND or PGND but

is recommended to be connected to PGND, the system GND plane(s), which has better heat radiation.

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