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MPXD2005VLU80R Datasheet(PDF) 25 Page - Freescale Semiconductor, Inc |
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MPXD2005VLU80R Datasheet(HTML) 25 Page - Freescale Semiconductor, Inc |
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25 / 130 page  Pinout and signal descriptions PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor 25 2.2 208 LQFP package pinout Figure 3 shows the pinout for the 208-pin LQFP package. Figure 3. 208-pin LQFP pinout PXD20 208 LQFP Top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 DCU_VSYNC_TCON2 / PG8 DCU_HSYNC_TCON1 / PG9 DCU_DE_TCON3 / PG10 eMIOS0[8] / eMIOS1[9] / PDI_HSYNC_VIU1 / PJ1 eMIOS0[9] / eMIOS1[14] / PDI_VSYNC_VIU0 / PJ2 VDDE_B VSS eMIOS0[13] / eMIOS0[17] / PDI4_VIU6 / PJ8 eMIOS0[12] / eMIOS1[22] / PDI5_VIU7 / PJ9 eMIOS0[11] / eMIOS1[17] / PDI6_VIU8 / PJ10 eMIOS0[10] / eMIOS1[15] / PDI7_VIU9 / PJ11 RXD_0 / CNRX_0 / PB1 TXD_0 / CNTX_0 / PB0 I2S_DO / CNRX_1 / PB10 SGM_MCLK / CNTX_1 / PB11 TCON4 / RXD_3 / CNRX_2 / PM3 TCON5 / TXD_3 / CNTX_2 / PM4 VSS VDDE_B VDDR VSSR VSUP_TEST VDD12 VSS VDDPLL VREG_BYPASS EXTAL XTAL VRC_CTRL RESET TCON6 / PDI13_VIU5 / CS2_2 / PL4 TCON7 / PDI14_VIU6 / CS1_2 / PL5 eMIOS1[18] / PDI15_VIU7 / CS0_2 / PL6 eMIOS1[19] / PDI16_VIU8 / SIN_2 / PL7 eMIOS1[20] / PDI17_VIU9 / SOUT_2 / PL8 eMIOS1[21] / PDI_PCLK / SCK_2 / PL9 VDDE_B VSS DCULITE_TAG / eMIOS1[10] / PDI8_VIU0 / PK2 DCULITE_DE / eMIOS1[11] / PDI9_VIU1 / PK3 DCULITE_HSYNC / eMIOS1[12] / PDI10_VIU2 / PK4 DCULITE_VSYNC / eMIOS1[13] / PDI11_VIU3 / PK5 DCULITE_PCLK / eMIOS1[9] / PDI12_VIU4 / PK6 TCON8 / DCULITE_R2 / RXD_2 / PK7 TCON9 / DCULITE_R3 / TXD_2 / PK8 TCON10 / DCULITE_R4 / I2S_DO / PK9 VSS VDDE_B TCK / PH0 TDI / PH1 TDO / PH2 TMS / PH3 VDDE_B PA13 / DCU_G5 / RSDS6M PA12 / DCU_G4 / RSDS6P PA11 / DCU_G3 / RSDS5M PA10 / DCU_G2 / RSDS5P PA9 / DCU_G1 /SDA_2 /eMIOS0[19]/RSDS4M PA8 / DCU_G0 / SCL_2 / eMIOS0[20] / RSDS4P PA7 / DCU_R7 / RSDS3M PA6 / DCU_R6 / RSDS3P VSS VDDE_B VREF_RSDS PA5 / DCU_R5 / RSDS2M PA4 / DCU_R4 / RSDS2P PA3 / DCU_R3 / RSRS1M PA2 / DCU_R2 / RSDS1P PA1 / DCU_R1 / SCL_1 / eMIOS0[17] / RSDS0M PA0 / DCU_R0 / SDA_1 / eMIOS0[18] / RSDS0P VDDE_B VSS VDD12 PE7 / M5C1P / SSD5_3 PE6 / M5C1M / SSD5_2 PE5 / M5C0P / SSD5_1 PE4 / M5C0M / SSD5_0 VSSM VDDM PE3 / M4C1P / SSD4_3 PE2 / M4C1M / SSD4_2 PE1 / M4C0P / SSD4_1 PE0 / M4C0M / SSD4_0 PD15 / M3C1P / SSD3_3 / eMIOS0[15] PD14 / M3C1M / SSD3_2 / eMIOS0[14] PD13 / M3C0P / SSD3_1 / eMIOS0[13] PD12 / M3C0M / SSD3_0 / eMIOS0[12] VSSM VDDM PD11 / M2C1P / SSD2_3 / eMIOS0[11] PD10 / M2C1M / SSD2_2 / eMIOS0[10] PD9 / M2C0P / SSD2_1 / eMIOS0[9] PD8 / M2C0M / SSD2_0 PD7 / M1C1P / SSD1_3 PD6 / M1C1M / SSD1_2 / eMIOS0[23] PD5 / M1C0P / SSD1_1 / eMIOS0[16] PD4 / M1C0M / SSD1_0 / eMIOS0[8] VSSM VDDM PD3 / M0C1P / SSD0_3 / eMIOS0[9] PD2 / M0C1M / SSD0_2 / eMIOS1[23] PD1 / M0C0P / SSD0_1 / eMIOS1[16] PD0 / M0C0M / SSD0_0 / eMIOS1[8] VDDE_B |
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