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MPXD2005VLU80R Datasheet(PDF) 33 Page - Freescale Semiconductor, Inc |
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MPXD2005VLU80R Datasheet(HTML) 33 Page - Freescale Semiconductor, Inc |
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33 / 130 page ![]() Pinout and signal descriptions PXD20 Microcontroller Data Sheet, Rev. 2 Preliminary—Subject to Change Without Notice Freescale Semiconductor 33 DDR_A[10] DRAM address [10] Output DDR PCR[212] Output, None C13 DDR_A[9] DRAM address [9] Output DDR PCR[211] Output, None B13 DDR_A[8] DRAM address [8] Output DDR PCR[210] Output, None A13 DDR_A[7] DRAM address [7] Output DDR PCR[209] Output, None B12 DDR_A[6] DRAM address [6] Output DDR PCR[208] Output, None A12 DDR_A[5] DRAM address [5] Output DDR PCR[207] Output, None D11 DDR_A[4] DRAM address [4] Output DDR PCR[206] Output, None A11 DDR_A[3] DRAM address [3] Output DDR PCR[205] Output, None D10 DDR_A[2] DRAM address [2] Output DDR PCR[204] Output, None C10 DDR_A[1] DRAM address [1] Output DDR PCR[203] Output, None B10 DDR_A[0] DRAM address [0] Output DDR PCR[202] Output, None A10 DRAM Bank Address DDR_BA[2] DRAM Bank Address[2] Output DDR PCR[220] Output, None A9 DDR_BA[1] DRAM Bank Address[1] Output DDR PCR[219] Output, None A8 DDR_BA[0] DRAM Bank Address[0] Output DDR PCR[218] Output, None A7 DRAM Control DDR_CAS Column Address Strobe Output DDR PCR[221] Output, None B6 DDR_RAS Row Address Strobe Output DDR PCR[227] Output, None B7 DDR_WEB Write Enable Output DDR PCR[228] Output, None B9 DDR_ODT DRAM On-die termination Output DDR PCR[226] Output, Pull Down D5 DDR_CLK DRAM Clock Output DDR PCR[225] Output, None C7 Table 6. DRAM interface pin summary (continued) Port pin1 Function I/O direction Pad type PCR RESET config2 Pin number 416 TEPBGA |
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