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RT5002 Datasheet(PDF) 36 Page - Richtek Technology Corporation

Part # RT5002
Description  7 1 Channel DC/DC PMU with Li-Ion Battery Charger for DSC
PDF  40 Pages
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Manufacturer  RICHTEK [Richtek Technology Corporation]
Direct Link  http://www.richtek.com
Logo RICHTEK - Richtek Technology Corporation

RT5002 Datasheet(HTML) 36 Page - Richtek Technology Corporation

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RT5002
36
DS5002-00
November 2011
www.richtek.com
Figure 4. Derating Curves for RT5002 Package
0.00
0.40
0.80
1.20
1.60
2.00
2.40
2.80
3.20
0
25
50
75
100
125
Ambient Temperature (
°C)
Four-Layer PCB
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX)
− TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and
θJAis the junction to ambient
thermal resistance.
For recommended operating condition specifications of
the RT5002, the maximum junction temperature is 125
°C
and TA is the ambient temperature. The junction to ambient
thermal resistance,
θJA, is layout dependent. For WQFN-
40L 5x5 packages, the thermal resistance,
θJA, is 36°C/
W on a standard JEDEC 51-7 four-layer thermal test board.
The maximum power dissipation at T
A
= 25
°C can be
calculated by the following formula :
PD(MAX) = (125
°C − 25°C) / (36°C/W) = 2.778W for
WQFN-40L 5x5 package
The maximum power dissipation depends on the operating
ambient temperature for fixed TJ(MAX) and thermal
resistance,
θJA. For the RT5002 package, the derating
curve in Figure 4 allows the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.
Layout Considerations
For the best performance of the RT5002, the following
PCB layout guidelines must be strictly followed.
}
Place the input and output capacitors as close as
possible to the input and output pins respectively for
good filtering.
}
Keep the main power traces as wide and short as
possible.
}
The switching node area connected to LX and inductor
should be minimized for lower EMI.
}
Place the feedback components as close as possible
to the FB pin and keep these components away from
the noisy devices.
}
Connect the GND and Exposed Pad to a strong ground
plane for maximum thermal dissipation and noise
protection.
}
The connection of RISETA should be isolated from other
noisy traces. A short wire is recommended to prevent
EMI and noise coupling.



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