AD9789BBCZ datasheet(38/76 Pages) AD

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AD9789

Rev. A | Page 38 of 76

Table 45. Mu Delay Control 3 Register (Address 0x39)

Bit

Bit Name

Description

MUDLY[0]

This bit is the LSB of the mu delay value. Along with Bits[7:0] in Register 0x3A, this bit configures the

programmable mu delay; the search algorithm begins at this specified mu delay value. In manual mode, the

MUDLY bits can be written to. In tracking mode, the sampled MUDLY value can be read back. Even though

there are 9 bits of resolution for this delay line value, the maximum allowable mu delay is 431 (0x1AF). The

optimal point to begin the search is in the middle of the delay line, or approximately 216 (0xD8).

[6:5]

SEARCH_DIR[1:0]

These bits configure the search direction, starting at the selected mu delay value.

00 = search down.

01 = search up.

10 = search up and down (optimal).

11 = invalid.

[4:0]

MUPHZ[4:0]

These bits specify the phase to be measured with the maximum allowable phase being 16 (10000). If a value

larger than 16 is loaded, the controller will not lock. When the desired phase is measured, the slope of the

phase measurement is calculated and compared to the configured slope, which is specified by the SLOPE bit

in Register 0x33[6]. For optimal ac performance, the best setting for the search is for a positive slope and a

phase value of 14 (01110).

Table 46. Mu Delay Control 4 Register (Address 0x3A)

Bit

Bit Name

Description

[7:0]

MUDLY[8:1]

Along with Bit 7 in Register 0x39, these bits configure the programmable mu delay; the search algorithm

begins at this specified mu delay value. In manual mode, the MUDLY bits can be written to. In tracking mode,

the sampled MUDLY value can be read back. Even though there are 9 bits of resolution for this delay line

value, the maximum allowable mu delay is 431 (0x1AF). The optimal point to begin the search is in the

middle of the delay line, or approximately 216 (0xD8).

Table 47. Full-Scale Current 1 Register (Address 0x3C)

Bit

Bit Name

Description

[7:0]

FSC[7:0]

Along with Bits[1:0] in Register 0x3D, this register sets the full-scale current for the DAC. For more information,

see the Voltage Reference section.

Setting (Includes Register 0x3D[1:0])

Full-Scale Current (mA)

0000000000

8.6

…

1000000000

20 (default)

…

1011010000

…

1111111111

32.1

Table 48. Full-Scale Current 2 Register (Address 0x3D)

Bit

Bit Name

Description

[7:2]

Reserved

Reserved.

[1:0]

FSC[9:8]

Along with the FSC[7:0] bits in Register 0x3C, these bits set the full-scale current for the DAC. For more infor-

mation, see Table 47 and the Voltage Reference section.

Table 49. Phase Detector Control Register (Address 0x3E)

Bit

Bit Name

Description

PHZ_PD

Powers down the phase detector. This bit is for factory use only; this bit should be set to 0.

Reserved

Reserved.

CMP_BST

Comparator boost. This bit is for factory use only; this bit should always be set to 1.

AUTO_CAL

This bit is for factory use only; this bit should always be set to 1.

[3:0]

PHZ_DET_BIAS[3:0]

These bits display the binary weighted current. Do not write to these bits (factory use only).

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