AD9789BBCZ datasheet(42/76 Pages) AD

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AD9789

Rev. A | Page 42 of 76

Sample Rate Converter

The purpose of the sample rate converter (SRC) is to provide

increased flexibility in the ratio of the input baud rate to the

DAC update rate. Each of the four channelization datapaths

contains a sample rate converter (SRC) that provides a data rate

conversion in the range of 0.5 to 1.0 inclusive. The rate conversion

factor is set by the ratio of two 24-bit values, P and Q. Figure 83

is a conceptual block diagram of the SRC. It can be thought of

as an interpolation block, followed by filtering and decimation

blocks.

Figure 83. Conceptual Block Diagram of the Sample Rate Converter

The values of P and Q are set by programming the P[23:0] and

Q[23:0] registers at Address 0x16 through Address 0x1B.

Table 51. Register Locations for Sample Rate Converter

Bits

Numerator (P)

Denominator (Q)

[23:16] (Byte 2)

[15:8] (Byte 1)

[7:0] (Byte 0)

The values of P and Q should be selected to satisfy the following

equation for the desired baud rate (fBAUD) and DAC clock fre-

quency (fDAC).

BAUD

DAC

16 ×

(1)

where I is the total interpolation ratio of the SRRC filter and the

five half-band interpolation filters.

If Equation 1 is satisfied, the long-term baud rate, fBAUD, is

exactly maintained. No residual frequency offset errors are

introduced by the rate conversion process.

The values of P and Q must be selected within the following

constraints:

≤

(2)

Q[23]

= 1

(3)

Equation 3 states that the value of Q must be shifted so that the

MSB of Q is set.

In most systems, the baud rate is a given, and the DAC sample

rate is selected so that it is high enough to support the signal

bandwidth and output frequency requirements. In many cases,

it is desirable to set the DAC clock rate to a multiple of a system

clock rate. The following example shows how P and Q can be

selected in such a system.

Example

A DOCSIS application has a master system clock that runs at a

frequency of fMASTER. Several channel baud rates are supported,

all of which are fractions of the master clock and can be

represented by the following equation:

MASTER

BAUD

(4)

Equation 1 must be satisfied for fBAUD to be exactly maintained.

To facilitate this, the DAC sampling frequency is selected to be a

multiple of fMASTER that satisfies the signal bandwidth and output

frequency requirements. For fMASTER = 10.24 MHz, a signal band-

width requirement of 32 MHz or greater, and a supported output

frequency band of up to 1 GHz, the following DAC sampling

frequency can be selected:

MHz

2293

224

MASTER

DAC

(5)

Inserting Equation 4 and Equation 5 into Equation 1 results in

Equation 6.

MASTER

224

(6)

Enabling the SRRC filter and four of the half-band interpolation

filters would result in the total interpolation factor, I, being equal

to 32. Substituting 32 for I and simplifying Equation 6 results in

Equation 7.

(7)

Recall that N and M are given by the required baud rate. For

example, assume a baud rate of 5.0569 MHz, which results from

M = 401 and N = 812.

MHz

0569

MHz

812

401

BAUD

(8)

P and Q can then be calculated from the numerator and

denominator of Equation 9.

1910

1634

6416

5684

401

812

(9)

Because the value of Q must be MSB justified, both numbers

can be shifted by 11 bits, resulting in the final P and Q values

of 0xB1A000 and 0xC80000, respectively.

Baseband Digital Upconverter

The digital upconverter enables each baseband channel to be

placed anywhere from dc to fDAC/16. The center frequency for

each of the four channels is register programmable through the

24-bit frequency tuning words, FTW 0 through FTW 3. For the

desired center frequency of each individual channel, the FTW

can be calculated as follows:

()1

−

⎟

⎠

⎞

⎜

⎝

⎛

DAC

CENTER

FTW

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