AD9789BBCZ datasheet(45/76 Pages) AD

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AD9789

Rev. A | Page 45 of 76

DIGITAL INTERFACE MODES

The AD9789 can be configured for two main digital interface

modes of operation:

•

Channelizer mode

•

Quadrature digital upconverter (QDUC ) mode

In channelizer mode (Register 0x20[3] = 0), the interface can be

configured for 4- to 32-bit bus widths and can accept up to four

channels of complex data. Any of the signal processing blocks in

the digital datapath can be used. The maximum baud rate

supported in channelizer mode is fDAC/48.

In QDUC mode (Register 0x20[3] = 1), the interface is fixed at

a 32-bit bus width and one channel of complex data. The available

signal processing methods are interpolation (16× to 512×), rate

conversion (0.5 to 1.0), and complex modulation. The maximum

baud rate supported in QDUC mode is fDAC/16.

In both channelizer and QDUC modes, the input data bus

can be configured to accept LVDS or CMOS data via the

CMOS_BUS pin (L14). If CMOS_BUS is pulled to 3.3 V, the

data bus is configured to accept CMOS inputs (D[31:0], P0,

and P1). If CMOS_BUS is pulled to 0 V, the bus is configured

to accept LVDS inputs (D[15:0]P, D[15:0]N, PARP, and PARN).

Two output signals are used to source data into the AD9789.

The first is the data clock output signal (DCO), which is

provided to clock data from the digital data source. DCO is a

divided-down version of DACCLK. The second is the frame sync

signal (FS), which is provided to request a new data-word. The

average frequency of the FS signal is equal to the symbol rate or

baud rate of the data. As with the input data bus, the DCO and

FS signals can be configured as LVDS or CMOS outputs via the

CMOS_CTRL pin (M14). If CMOS_CTRL is pulled to 3.3 V,

DCO and FS are output as CMOS signals on the P14 and N14

pins (CMOS_DCO and CMOS_FS), respectively. If CMOS_CTRL

is pulled to 0 V, DCO and FS are output as LVDS signals on the

N13, P13, L13, and M13 pins (DCOP, DCON, FSP, and FSN),

respectively.

Channelizer Mode

In channelizer mode, the digital interface has programmable

bus width, data width, and data format. The bus width, which is

the physical width of the digital data bus at the input of the

AD9789, can be set to a 4-, 8-, 16-, or 32-bit wide interface. The

data width, which is the internal width of the data at the input

to the digital datapath, can be set to an 8-bit or 16-bit word. The

data format can be programmed for real or complex data. A list

of supported interface modes is shown in Table 55.

UP TO

32 BITS

CMOS

0TO 15

LVDS

RISE

CMOS

16 TO 31

LVDS

FALL

UP TO

32 BITS

UP TO

32 BITS

UP TO

32 BITS

DCO

SUM

SCALE

BPF

CLK

CTL

fDAC

BPF

fC = 0 TO

fDAC/2

fDAC

16 TO 1024

DATA-

PATH

DATA-

PATH

DATA-

PATH

DATA-

PATH

Figure 92. Channelizer Mode

Table 55. Interface Configurations Supported

in Channelizer Mode

First Input

Block Enabled

Bus Width

Reg. 0x21[6:5]

Data Width

Reg. 0x21[4]

Data Format

Reg. 0x21[3]

QAM Encoder

32 bits

8 bits

Real

16 bits

8 bits

Real

8 bits

Real

4 bits

8 bits

Real

SRRC Filter

32 bits

8 bits

Complex

16 bits

8 bits

Complex

8 bits

Complex

4 bits

8 bits

Complex

Interpolation

32 bits

16 bits

Complex

Filter

16 bits

Complex

8 bits

16 bits

Complex

If the QAM encoder is the first block enabled in the datapath,

the data width should be set to an 8-bit word and real data

format. If the SRRC filter is the first block enabled in the

datapath, the data width should be set to an 8-bit word and

complex data format. If both the QAM encoder and the SRRC

filters are bypassed, the data width should be set to a 16-bit

word and complex data format.

Pin Mapping in Channelizer Mode

In CMOS mode (CMOS_BUS and CMOS_CTRL pins = 3.3 V),

the various interface width options are mapped to the AD9789

input pins as shown in Table 56.

Table 56. CMOS Pin Assignments for Various Interface Widths

Interface Width

Pin Assignments

BUSWDTH[1:0]

4 bits

D[3:0]

8 bits

D[7:0]

16 bits

D[15:0]

32 bits

D[31:0]

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