AD9789BBCZ datasheet(68/76 Pages) AD

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AD9789

Rev. A | Page 68 of 76

CHANNELIZER MODE PIN MAPPING FOR CMOS AND LVDS

Table 93 lists the available combinations of data input configu-

ration parameters when the AD9789 is in channelizer mode.

Many of these configurations require multiple clocks to load all

channels. All of these configurations are described in detail in

Table 96 and Table 97.

Table 94 and Table 95, along with Figure 128 and Figure 129,

describe CMOS and LVDS data input pin mapping. CMOS

mode is always single data rate and samples on the rising edge

of DSC. LVDS mode is single data rate (SDR) for bus widths

of 4 bits through 16 bits and double data rate (DDR) for a bus

width of 32 bits.

Table 93. Data Input Configurations for Channelizer Mode

Bus Width

Data Width

Data Format

Real

Complex

Real

Complex

Real

Complex

Real

Complex

Table 94. CMOS Pin Assignments for Various Interface Widths

Interface Width

Pin Assignments

BUSWDTH[1:0]

4 bits

D[3:0]

8 bits

D[7:0]

16 bits

D[15:0]

32 bits

D[31:0]

Table 95. LVDS Pin Assignments for Various Interface Widths

Interface Width

Pin Assignments

BUSWDTH[1:0]

4 bits

D[3:0]P, D[3:0]N

8 bits

D[7:0]P, D[7:0]N

16 bits

D[15:0]P, D[15:0]N

32 bits

D[15:0]P, D[15:0]N rising

edge and falling edge

CMOS_BUS

CMOS_CTRL

CMOS_FS

CMOS_DCO

31 27 23 19 15 11

30 26 22 18 14 10

29 25 21 17 13

28 24 20 16 12

D[31:0] CMOS DATA INPUTS

PARITY AND CONTROL INPUTS

Figure 128. CMOS Data Input Pin Mapping

PARN

PARP

FSP

FSN

DCOP

DCON

P+

15 13 11

P–

15 13 11

14 12 10

+LVDS

14 –LVDS

Figure 129. LVDS Data Input Pin Mapping

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