AD9789BBCZ datasheet(57/76 Pages) AD

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AD9789

Rev. A | Page 57 of 76

Finally, when measuring performance for CMTS and other

digital TV applications, it is advantageous to insert a 1 dB,

1.2 GHz Chebyshev low-pass filter between the DAC and the

transformer to better control the impedance seen at the DAC

core. This helps to decrease the folded back harmonics for

higher frequency outputs. The optimal transformer for CMTS

measurements is the JTX-2-10T, which consists of a balun and

center-tapped transformer in a single package. This output stage

is shown in Figure 112.

The buffer, in turn, can be easily driven from lower level signals

such as CML or attenuated PECL that might be encountered on

a PCB. This buffer also provides very low, 100 fs added random

jitter, which is important to obtain the optimal ac performance

from the AD9789. A functional block diagram of the ADCLK914

is shown in Figure 113. Figure 114 shows the recommended

schematic for the ADCLK914/AD9789 interface. Refer to the

ADCLK914 data sheet for more information. Any time that the

noise floor from the DAC cannot meet the specifications in this

data sheet, the clock should be examined.

90Ω

70Ω

IOUTP

5.6nH

IOUTN

4.7pF

2.2pF

4.7pF

JTX-2-10T

50Ω

VREF

VCC

VEE

50Ω

ADCLK914

Figure 112. Recommended Transformer Output Stage

for CMTS Measurements

Traces from the DAC to the transformer should be 50 Ω imped-

ance to ground each in Figure 110 and Figure 112 and 25 Ω to

ground each in Figure 111 to avoid unnecessary parasitics.

Figure 113. ADCLK914 Functional Block Diagram

The internal 50 Ω resistors shown at the ADCLK914 inputs are

rated to carry currents from PECL or CML drivers. The VT pin

can be connected to VCC, a PECL current sink, or the internal

VREF, or it can be left floating depending on the source. The

common-mode input range of the ADCLK914 does not include

LVDS voltage levels, so ac coupling is required in that case.

CLOCKING THE AD9789

To provide the required signal swing for the internal clock

receiver of the AD9789, it is necessary to use an external clock

buffer chip to drive the CLKP and CLKN inputs. These high

level, high slew rate signals should not be routed any distance

on a PCB. The recommended clock buffer for this application

is the ADCLK914. This ultrafast clock buffer is capable of

providing 1.9 V out of each side into a 50 Ω load terminated

to VCC (3.3 V) for a total differential swing of 3.8 V.

GND

16 15 14 13

56 78

C31

0.1µF

C0402

GND

C32

0.01µF

C0402

GND

C33

0.1µF

C0402

GND

C34

0.01µF

C0402

GND

ADCLK914 SUPPLY DECOUPLING

VCC33

CLKP

CLKN

R13

49.9Ω

R15

49.9Ω

R14

49.9Ω

R17

100Ω

R0402

C99

2400pF

C0803H50

C102

2400pF

C0803H50

ADCLK914

GND

C83

0.01µF

C81

0.01µF

C82

0.01µF

PSTRNKPE4117

Figure 114. ADCLK914/AD9789 Interface Circuit for Use with a Lab Generator

AD9789BBCZ Datasheet(PDF) 57 Page - Analog Devices

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