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Z8F0113 Datasheet(PDF) 71 Page - Zilog, Inc. |
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Z8F0113 Datasheet(HTML) 71 Page - Zilog, Inc. |
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71 / 245 page  PS024315-1011 P R E L I M I N A R Y Architecture Z8 Encore! XP® F0823 Series Product Specification 56 Architecture Figure 8 displays the interrupt controller block diagram. Operation This section describes the operational aspects of the following functions. Master Interrupt Enable: see page 56 Interrupt Vectors and Priority: see page 57 Interrupt Assertion: see page 57 Software Interrupt Assertion: see page 58 Watchdog Timer Interrupt Assertion: see page 58 Master Interrupt Enable The master interrupt enable bit (IRQE) in the Interrupt Control Register globally enables and disables interrupts. Interrupts are globally enabled by any of the following actions: • Execution of an Enable Interrupt (EI) instruction Figure 8. Interrupt Controller Block Diagram Vector IRQ Request High Priority Medium Priority Low Priority Priority Mux Port Interrupts Internal Interrupts |
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