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Z8F0113 Datasheet(PDF) 83 Page - Zilog, Inc. |
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Z8F0113 Datasheet(HTML) 83 Page - Zilog, Inc. |
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83 / 245 page  PS024315-1011 P R E L I M I N A R Y Interrupt Control Register Definitions Z8 Encore! XP® F0823 Series Product Specification 68 Interrupt Control Register The Interrupt Control (IRQCTL) Register (Table 50) contains the master enable bit for all interrupts. Table 50. Interrupt Control Register (IRQCTL) Bit 7 6 5 4 3 2 1 0 Field IRQE Reserved RESET 00000000 R/W R/W RRRRRR R Address FCFH Bit Description [7] IRQE Interrupt Request Enable This bit is set to 1 by executing an Enable Interrupts (EI) or Interrupt Return (IRET) instruction, or by a direct register write of a 1 to this bit. It is reset to 0 by executing a DI instruction, eZ8 CPU acknowledgement of an interrupt request, reset or by a direct register write of a 0 to this bit. 0 = Interrupts are disabled. 1 = Interrupts are enabled. [6:0] Reserved These bits are reserved and must be programmed to 0000000 when read. |
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