Z8F0113 datasheet(80/245 Pages) ZILOG

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PS024315-1011

P R E L I M I N A R Y

Interrupt Control Register Definitions

Z8 Encore! XP® F0823 Series

Product Specification

IRQ2 Enable High and Low Bit Registers

Table 45 describes the priority control for IRQ2. The IRQ2 Enable High and Low Bit reg-

isters (Table 46 and Table 47) form a priority encoded enabling for interrupts in the Inter-

rupt Request 2 register. Priority is generated by setting bits in each register.

Table 45. IRQ2 Enable and Priority Encoding

IRQ2ENH[x]IRQ2ENL[x] Priority

Description

Disabled

Level 1

Low

Level 2

Nominal

Level 3

High

Note: where x indicates the register bits from 0–7.

Table 46. IRQ2 Enable High Bit Register (IRQ2ENH)

Bit

Field

Reserved

C3ENH

C2ENH

C1ENH

C0ENH

RESET

00000000

R/W

R/WR/W

R/WR/WR/WR/WR/WR/W

Address

FC7H

Bit

Description

[7:4]

Reserved

These bits are reserved and must be programmed to 0000.

[3]



C3ENH

Port C3 Interrupt Request Enable High Bit

[2]



C2ENH

Port C2 Interrupt Request Enable High Bit

[1]



C1ENH

Port C1 Interrupt Request Enable High Bit

[0]



C0ENH

Port C0 Interrupt Request Enable High Bit

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