DSPIC33FJ06GS201TESLASHMM datasheet(202/346 Pages) MICROCHIP

202 / 346 page

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

DS70318D-page 200

Preliminary

PTCON: PWM TIME BASE CONTROL REGISTER

R/W-0

U-0

R/W-0

HS/HC-0

R/W-0

PTEN

—

PTSIDL

SESTAT

SEIEN

EIPU(1)

SYNCPOL(1) SYNCOEN(1)

bit 15

bit 8

R/W-0

U-0

R/W-0

SYNCEN(1)

—

SYNCSRC<1:0>(1)

SEVTPS<3:0>(1)

bit 7

bit 0

Legend:

HC = Hardware Clearable bit

HS = Hardware Settable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

PTEN:

PWM Module Enable bit

= PWM module is enabled

= PWM module is disabled

bit 14

Unimplemented:

Read as ‘0’

bit 13

PTSIDL:

PWM Time Base Stop in Idle Mode bit

= PWM time base halts in CPU Idle mode

= PWM time base runs in CPU Idle mode

bit 12

SESTAT:

Special Event Interrupt Status bit

= Special event interrupt is pending

= Special event interrupt is not pending

bit 11

SEIEN:

Special Event Interrupt Enable bit

= Special event interrupt is enabled

= Special event interrupt is disabled

bit 10

EIPU:

Enable Immediate Period Updates bit(1)

= Active Period register is updated immediately

= Active Period register updates occur on PWM cycle boundaries

bit 9

SYNCPOL:

Synchronization Input/Output Polarity bit(1)

= SYNCIx and SYNCO polarity is inverted (active-low)

= SYNCIx and SYNCO are active-high

bit 8

SYNCOEN:

Primary Time Base Sync Enable bit(1)

= SYNCO output is enabled

= SYNCO output is disabled

bit 7

SYNCEN:

External Time Base Synchronization Enable bit(1)

= External synchronization of primary time base is enabled

= External synchronization of primary time base is disabled

bit 6

Unimplemented:

Read as ‘0’

bit 5-4

SYNCSRC<1:0>:

Synchronous Source Selection bits(1)

= SYNCI1

= SYNCI2

= Reserved

bit 3-0

SEVTPS<3:0>:

PWM Special Event Trigger Output Postscaler Select bits(1)

0000

= 1:1 Postscaler generates a Special Event Trigger on every compare match event

0001

= 1:2 Postscaler generates a Special Event Trigger on every second compare match event

•

1111

= 1:16 Postscaler generates a Special Event Trigger trigger on every sixteenth compare match event

Note 1:

These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user

application must program the period register with a value that is slightly larger than the expected period of

the external synchronization input signal.

DSPIC33FJ06GS201TE/MM Datasheet(PDF) 202 Page - Microchip Technology

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