DSPIC33FJ06GS201TESLASHMM datasheet(205/346 Pages) MICROCHIP

205 / 346 page

Preliminary

DS70318D-page 203

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

PWMCONx: PWMx CONTROL REGISTER

HS/HC-0

R/W-0

FLTSTAT(1)

CLSTAT(1)

TRGSTAT

FLTIEN

CLIEN

TRGIEN

ITB(3)

MDCS(3)

bit 15

bit 8

R/W-0

U-0

R/W-0

DTC<1:0>

—

—CAM(2,3)

XPRES(4)

IUE

bit 7

bit 0

Legend:

HC = Hardware Clearable bit

HS = Hardware Settable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

FLTSTAT:

Fault Interrupt Status bit(1)

= Fault interrupt is pending

= No Fault interrupt is pending. This bit is cleared by setting FLTIEN = 0.

bit 14

CLSTAT:

Current-Limit Interrupt Status bit(1)

= Current-limit interrupt is pending

= No current-limit interrupt is pending. This bit is cleared by setting CLIEN = 0.

bit 13

TRGSTAT:

Trigger Interrupt Status bit

= Trigger interrupt is pending

= No trigger interrupt is pending. This bit is cleared by setting TRGIEN = 0.

bit 12

FLTIEN:

Fault Interrupt Enable bit

= Fault interrupt is enabled

= Fault interrupt is disabled and the FLTSTAT bit is cleared

bit 11

CLIEN:

Current-Limit Interrupt Enable bit

= Current-limit interrupt enabled

= Current-limit interrupt disabled and the CLSTAT bit is cleared

bit 10

TRGIEN:

Trigger Interrupt Enable bit

= A trigger event generates an interrupt request

= Trigger event interrupts are disabled and the TRGSTAT bit is cleared

bit 9

ITB:

Independent Time Base Mode bit(3)

= PHASEx/SPHASEx register provides time base period for this PWM generator

= PTPER register provides timing for this PWM generator

bit 8

MDCS:

Master Duty Cycle Register Select bit(3)

= MDC register provides duty cycle information for this PWM generator

= PDCx/SDCx register provides duty cycle information for this PWM generator

bit 7-6

DTC<1:0>:

Dead-Time Control bits

= Positive dead time actively applied for all output modes

= Negative dead time actively applied for all output modes

= Dead-time function is disabled

= Reserved

bit 5-3

Unimplemented:

Read as ‘0’

Note 1:

Software must clear the interrupt status here and the corresponding IFS bit in the interrupt controller.

The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the

CAM bit is ignored.

These bits should be changed only when PTEN = 0. Changing the clock selection during operation will

yield unpredictable results.

To operate in External Period Reset mode, configure FCLCONx<CLMOD> = 0 and PWMCONx<ITB> = 1.

DSPIC33FJ06GS201TE/MM Datasheet(PDF) 205 Page - Microchip Technology

DSPIC33FJ06GS201TE/MM Datasheet(HTML) 205 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL