DSPIC33FJ06GS201TESLASHMM datasheet(203/346 Pages) MICROCHIP

203 / 346 page

Preliminary

DS70318D-page 201

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

PTCON2: PWM CLOCK DIVIDER SELECT REGISTER

U-0

—

bit 15

bit 8

U-0

R/W-0

—

—PCLKDIV<2:0>(1)

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-3

Unimplemented:

Read as ‘0’

bit 2-0

PCLKDIV<2:0>:

PWM Input Clock Prescaler (Divider) Select bits(1)

000

= Divide by 1, maximum PWM timing resolution (power-on default)

001

= Divide by 2, maximum PWM timing resolution

010

= Divide by 4, maximum PWM timing resolution

011

= Divide by 8, maximum PWM timing resolution

100

= Divide by 16, maximum PWM timing resolution

101

= Divide by 32, maximum PWM timing resolution

110

= Divide by 64, maximum PWM timing resolution

111

= Reserved

Note 1:

These bits should be changed only when PTEN = 0. Changing the clock selection during operation will

yield unpredictable results.

PTPER: PWM MASTER TIME BASE REGISTER(1)

R/W-1

PTPER <15:8>

bit 15

bit 8

R/W-1

R/W-0

PTPER <7:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-0

PTPER<15:0>:

PWM Master Time Base (PMTMR) Period Value bits

Note 1:

The minimum value that can be loaded into the PTPER register is 0x0010 and the maximum value is

0xFFF8.

DSPIC33FJ06GS201TE/MM Datasheet(PDF) 203 Page - Microchip Technology

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