DSPIC33FJ06GS201TESLASHMM datasheet(333/346 Pages) MICROCHIP

333 / 346 page

Preliminary

DS70318D-page 331

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

Section 16.0 “Inter-Integrated

Circuit (I2C™)”

Removed the following sections, which are now available in the related

section of the dsPIC33F Family Reference Manual:

• 16.3 “I2C Interrupts”

• 16.4 “Baud Rate Generator” (retained Figure 16-1: I2C Block Diagram)

• 16.5 “I2C Module Addresses

• 16.6 “Slave Address Masking”

• 16.7 “IPMI Support”

• 16.8 “General Call Address Support”

• 16.9 “Automatic Clock Stretch”

• 16.10 “Software Controlled Clock Stretching (STREN = 1)”

• 16.11 “Slope Control”

• 16.12 “Clock Arbitration”

• 16.13 “Multi-Master Communication, Bus Collision, and Bus Arbitration

Section 17.0 “Universal

Asynchronous Receiver Transmitter

(UART)”

Removed the following sections, which are now available in the related

section of the dsPIC33F Family Reference Manual:

• 17.1 “UART Baud Rate Generator”

• 17.2 “Transmitting in 8-bit Data Mode

• 17.3 “Transmitting in 9-bit Data Mode

• 17.4 “Break and Sync Transmit Sequence”

• 17.5 “Receiving in 8-bit or 9-bit Data Mode”

• 17.6 “Flow Control Using UxCTS and UxRTS Pins”

• 17.7 “Infrared Support”

Removed IrDA references and Note 1, and updated the bit and bit value

descriptions for UTXINV (UxSTA<14>) in the UARTx Status and Control

Section 18.0 “High-Speed 10-bit

Analog-to-Digital Converter (ADC)”

Updated bit value information for A/D Control Register (see Register 18-1).

Updated TRGSRC6 bit value for Timer1 period match in the A/D Convert

Pair Control Register 3 (see Register 18-8).

TABLE A-1:

MAJOR SECTION UPDATES (CONTINUED)

Section Name

Update Description

DSPIC33FJ06GS201TE/MM Datasheet(PDF) 333 Page - Microchip Technology