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DSPIC33FJ06GS201TE/MM Datasheet(PDF) 102 Page - Microchip Technology

Part # DSPIC33FJ06GS201TE/MM
Description  High-Performance, 16-bit Digital Signal Controllers
PDF  346 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

DSPIC33FJ06GS201TE/MM Datasheet(HTML) 102 Page - Microchip Technology

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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
DS70318D-page 100
Preliminary
© 2009 Microchip Technology Inc.
REGISTER 7-1:
SR: CPU STATUS REGISTER(1)
REGISTER 7-2:
CORCON: CORE CONTROL REGISTER(1)
R-0
R-0
R/C-0
R/C-0
R-0
R/C-0
R -0
R/W-0
OA
OB
SA
SB
OAB
SAB
DA
DC
bit 15
bit 8
R/W-0(3)
R/W-0(3)
R/W-0(3)
R-0
R/W-0
R/W-0
R/W-0
R/W-0
IPL2(2)
IPL1(2)
IPL0(2)
RA
N
OV
Z
C
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
U = Unimplemented bit, read as ‘0’
S = Settable bit
W = Writable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
IPL<2:0>:
CPU Interrupt Priority Level Status bits(2)
111
= CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110
= CPU Interrupt Priority Level is 6 (14)
101
= CPU Interrupt Priority Level is 5 (13)
100
= CPU Interrupt Priority Level is 4 (12)
011
= CPU Interrupt Priority Level is 3 (11)
010
= CPU Interrupt Priority Level is 2 (10)
001
= CPU Interrupt Priority Level is 1 (9)
000
= CPU Interrupt Priority Level is 0 (8)
Note 1:
For complete register details, see Register 3-1.
2:
The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3:
The IPL<2:0> status bits are read-only when NSTDIS (INTCON1<15>) = 1.
U-0
U-0
U-0
U-0
R/W-0
R-0
R-0
R-0
—
—
—
US
EDT
DL<2:0>
bit 15
bit 8
R/W-0
R/W-0
R/W-1
R/W-0
R/C-0
R/W-0
R/W-0
R/W-0
SATA
SATB
SATDW
ACCSAT
IPL3(2)
PSV
RND
IF
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
-n = Value at POR
‘1’ = Bit is set
0’ = Bit is cleared
‘x = Bit is unknown
U = Unimplemented bit, read as ‘0’
bit 3
IPL3:
CPU Interrupt Priority Level Status bit 3(2)
1
= CPU Interrupt Priority Level is greater than 7
0
= CPU Interrupt Priority Level is 7 or less
Note 1:
For complete register details, see Register 3-2.
2:
The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.



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