DSPIC33FJ06GS201TESLASHMM datasheet(103/346 Pages) MICROCHIP

103 / 346 page

Preliminary

DS70318D-page 101

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

INTCON1: INTERRUPT CONTROL REGISTER 1

R/W-0

NSTDIS

OVAERR

OVBERR

COVAERR

COVBERR

OVATE

OVBTE

COVTE

bit 15

bit 8

R/W-0

U-0

R/W-0

U-0

SFTACERR

DIV0ERR

—

MATHERR

ADDRERR

STKERR

OSCFAIL

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

NSTDIS:

Interrupt Nesting Disable bit

= Interrupt nesting is disabled

= Interrupt nesting is enabled

bit 14

OVAERR:

Accumulator A Overflow Trap Flag bit

= Trap was caused by overflow of Accumulator A

= Trap was not caused by overflow of Accumulator A

bit 13

OVBERR:

Accumulator B Overflow Trap Flag bit

= Trap was caused by overflow of Accumulator B

= Trap was not caused by overflow of Accumulator B

bit 12

COVAERR:

Accumulator A Catastrophic Overflow Trap Flag bit

= Trap was caused by catastrophic overflow of Accumulator A

= Trap was not caused by catastrophic overflow of Accumulator A

bit 11

COVBERR:

Accumulator B Catastrophic Overflow Trap Flag bit

= Trap was caused by catastrophic overflow of Accumulator B

= Trap was not caused by catastrophic overflow of Accumulator B

bit 10

OVATE:

Accumulator A Overflow Trap Enable bit

= Trap overflow of Accumulator A

= Trap disabled

bit 9

OVBTE:

Accumulator B Overflow Trap Enable bit

= Trap overflow of Accumulator B

= Trap disabled

bit 8

COVTE:

Catastrophic Overflow Trap Enable bit

= Trap on catastrophic overflow of Accumulator A or B enabled

= Trap disabled

bit 7

SFTACERR:

Shift Accumulator Error Status bit

= Math error trap was caused by an invalid accumulator shift

= Math error trap was not caused by an invalid accumulator shift

bit 6

DIV0ERR:

Arithmetic Error Status bit

= Math error trap was caused by a divide by zero

= Math error trap was not caused by a divide by zero

bit 5

Unimplemented:

Read as ‘0’

bit 4

MATHERR:

Arithmetic Error Status bit

= Math error trap has occurred

= Math error trap has not occurred

bit 3

ADDRERR:

Address Error Trap Status bit

= Address error trap has occurred

= Address error trap has not occurred

DSPIC33FJ06GS201TE/MM Datasheet(PDF) 103 Page - Microchip Technology

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