PSD813F2 datasheet(16/128 Pages) STMICROELECTRONICS

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Pin description

PSD8XXFX

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Doc ID 7833 Rev 7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

I/O

These pins make up port A. These port pins are configurable and can have the

following functions:

MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellAB0-7) outputs.

Inputs to the PLDs.

Latched address outputs (see Table 7).

Address inputs. For example, PA0-3 could be used for A0-A3 when using an 80C51XA

in burst mode.

As the data bus inputs D0-D7 for non-multiplexed address/data bus MCUs.

D0/A16-D3/A19 in M37702M2 mode.

Peripheral I/O mode.

Note: PA0-PA3 can only output CMOS signals with an option for high slew rate.

However, PA4-PA7 can be configured as CMOS or Open Drain outputs.

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

I/O

These pins make up port B. These port pins are configurable and can have the

following functions:

MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellAB0-7 or McellBC0-7) outputs.

Inputs to the PLDs.

Latched address outputs (see Table 7).

Note: PB0-PB3 can only output CMOS signals with an option for high slew rate.

However, PB4-PB7 can be configured as CMOS or Open Drain outputs.

PC0

I/O

PC0 pin of port C. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellBC0) output.

Input to the PLDs.

TMS input(2) for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

PC1

I/O

PC1 pin of port C. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellBC1) output.

Input to the PLDs.

TCK input(2) for the JTAG Serial Interface.

This pin can be configured as a CMOS or Open Drain output.

PC2

I/O

PC2 pin of port C. This port pin can be configured to have the following functions:

MCU I/O – write to or read from a standard output or input port.

CPLD macrocell (McellBC2) output.

Input to the PLDs.

This pin can be configured as a CMOS or Open Drain output.

Table 3.

PLCC52 pin description (1) (continued)

Pin name

Type

Description

Obsolete

Product(s)

- Obsolete

Product(s)

PSD813F2 Datasheet(PDF) 16 Page - STMicroelectronics

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