PSD813F2 datasheet(50/128 Pages) STMICROELECTRONICS

50 / 128 page

PLDS

PSD8XXFX

50/128

Doc ID 7833 Rev 7

14.2

Decode PLD (DPLD)

The DPLD, shown in Figure 13, is used for decoding the address for internal and external

components. The DPLD can be used to generate the following decode signals:

●

8 Sector Select (FS0-FS7) signals for the primary Flash memory (three product terms

each)

●

4 Sector Select (CSBOOT0-CSBOOT3) signals for the secondary Flash memory (three

product terms each)

●

1 internal SRAM Select (RS0) signal (two product terms)

●

1 internal CSIOP Select (PSD Configuration register) signal

●

1 JTAG Select signal (enables JTAG on port C)

●

2 internal Peripheral Select signals

(Peripheral I/O mode).

Figure 13.

DPLD logic array

(INPUTS)

(24)

(8)

(16)

(1)

PDN (APD OUTPUT)

I /O PORTS (PORT A,B,C)

(8)

PGR0 - PGR7

(8)

MCELLAB.FB [7:0] (FEEDBACKS)

MCELLBC.FB [7:0] (FEEDBACKS)

A[15:0]

(3)

PD[2:0] (ALE,CLKIN,CSI)

CNTRL[2:0] (READ/WRITE CONTROL SIGNALS)

(1)

RESET

RD_BSY

RS0

CSIOP

PSEL0

PSEL1

8 PRIMARY FLASH

MEMORY SECTOR SELECTS

SRAM SELECT

I/O DECODER

SELECT

PERIPHERAL I/O MODE

SELECT

CSBOOT 0

CSBOOT 1

CSBOOT 2

CSBOOT 3

FS0

FS7

JTAGSEL

AI02873D

FS1

FS2

FS3

FS6

FS5

FS4

Obsolete

Product(s)

- Obsolete

Product(s)

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