IO96NDB2V1 datasheet(144/242 Pages) MICROSEMI

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ProASIC3L DC and Switching Characteristics

2-128

Revision 13

Global Tree Timing Characteristics

Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not

include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven

and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer

to the "Clock Conditioning Circuits" section on page 2-132. Table 2-204 to Table 2-210 on page 2-131

present minimum and maximum global clock delays within each device. Minimum and maximum delays

are measured with minimum and maximum loading.

Timing Characteristics

Table 2-204 • A3P250L Global Resource – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter

Description

–1

Std.

Units

Min.1 Max.2 Min.1 Max.2

tRCKL

Input Low Delay for Global Clock

0.82

1.06

0.96

1.25

tRCKH

Input High Delay for Global Clock

0.80

1.09

0.94

1.28

tRCKMPWH

Minimum Pulse Width High for Global Clock

0.75

0.88

tRCKMPWL

Minimum Pulse Width Low for Global Clock

0.85

1.00

tRCKSW

Maximum Skew for Global Clock

0.29

0.34

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

Table 2-205 • A3P250L Global Resource – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V

Parameter

Description

–1

Std.

Units

Min.1 Max.2 Min.1 Max.2

tRCKL

Input Low Delay for Global Clock

1.40

1.68

1.64

1.97

tRCKH

Input High Delay for Global Clock

1.38

1.71

1.62

2.01

tRCKMPWH

Minimum Pulse Width High for Global Clock

1.05

1.24

tRCKMPWL

Minimum Pulse Width Low for Global Clock

1.23

1.44

tRCKSW

Maximum Skew for Global Clock

0.33

0.39

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating

values.

IO96NDB2V1 Datasheet(PDF) 144 Page - Microsemi Corporation

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