AT25DF641_13 datasheet(33/56 Pages) ETC2

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AT25DF641

3680F–DFLASH–4/10

If the device is powered-down during the OTP Security Register program cycle, then the contents of the 64-byte

user programmable portion of the OTP Security Register cannot be guaranteed and cannot be programmed

again.

The Program OTP Security Register command utilizes the internal 256-buffer for processing. T herefore, the

contents of the buffer will be altered from its previous state when this command is issued.

Figure 9-4.

Program OTP Security Register

SCK

MS B

37 38

31 32

29 30

OP C ODE

HIG H-IMP E DANC E

MS B

ADDR E S S B ITS A23-A0

DATA IN B Y TE 1

MS B

DATA IN B Y TE n

9.5.

Read OTP Security Register

The OTP Security Register can be sequentially read in a similar fashion to the Read Array operation up to the

maximum clock frequency specified by fMAX. To read the OTP Security Register, the

pin must first be asserted

and the opcode of 77h must be clocked into the device. After the opcode has been clocked in, the three address

bytes must be clocked in to specify the starting address location of the first byte to read within the OTP Security

be output.

After the three address bytes and the dummy bytes have been clocked in, additional clock cycles will result in

OTP Security Register data being output on t he SO pin. When the last byte (00007Fh) of the OTP Security

delays will be incurred when wrapping around from the end of the register to the beginning of the register.

Deasserting the

pin will terminate the read operation and put the SO pin into a high-impedance state. The

pin can be deasserted at any time and does not require that a full byte of data be read.

Figure 9-5.

Read OTP Security Register

SCK

M S B

10 11

31 32

29 30

O P C O DE

M S B

ADDR E S S B IT S A23-A0

M S B

DO N'T C AR E

DAT A B Y T E 1

HIG H-IMP E DANC E

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