AT25DF641_13 datasheet(43/56 Pages) ETC2

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AT25DF641

3680F–DFLASH–4/10

11.3. Deep Power-Down

During normal operation, the device will be placed in the standby mode to consume less power as long as the

pin remains deasserted and no internal operation is in progress. The Deep Power-Down command offers the

ability to place the device into an even lower power consumption state called the Deep Power-Down mode.

When the device is in the Deep Power-Down mode, all commands including the Read Status Register command

will be ignored with the exception of the Resume from Deep Power-Down command. Since all commands will be

ignored, the mode can be used as an extra protection mechanism against program and erase operations.

Entering the Deep Power-Down mode is accomplished by simply asserting the

pin, clocking in the opcode of

B9h, and then deasserting the

pin. Any additional data clocked into the device after the opcode will be

ignored. When the

pin is deasserted, the device will enter the Deep Power-Down mode within the maximum

time of tEDPD.

The complete opcode must be clocked in before the

pin is deasserted, and the

pin must be deasserted on

an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and return to the

standby mode once the

pin is deasserted. In addition, the device will default to the standby mode after a

power-cycle.

The Deep Power-Down command will be ignored if an internally self-timed operation such as a program or erase

cycle is in progress. The Deep Power-Down command must be reissued after the internally self-timed operation

has been completed in order for the device to enter the Deep Power-Down mode.

Figure 11-3.

Deep Power-Down

SCK

MS B

OP C ODE

HIG H-IMP E DANC E

S tandby Mode C urrent

Active C urrent

Deep P ower-Down Mode C urrent

tEDPD

ICC

AT25DF641 Datasheet(PDF) 43 Page - List of Unclassifed Manufacturers