10

AT25DF512C

DS-25DF512C–030A–4/2014

device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset

back to the logical “0” state if the program cycle aborts due to an incomplete address being sent, an incomplete byte of

data being sent, the CS pin being deasserted on uneven byte boundaries, or because the memory location to be

programmed is protected.

While the device is programming, the Status Register can be read and will indicate that the device is busy. For faster

throughput, it is recommended that the Status Register be polled rather than waiting the t

data bytes have finished programming. At some point before the program cycle completes, the WEL bit in the Status

Register will be reset back to the logical “0” state.

The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program

properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.

Figure 8-1.

Byte Program

Figure 8-2.

Page Program

8.2

Page Erase

The Page Erase command can be used to individually erase any page in the main memory array. The Main Memory

Byte/Page Program command can be utilized at a later time.

To perform a Page Erase with the standard page size (256 bytes), an opcode of 81h must be clocked into the device

followed by three address bytes comprised of eight dummy bits, 8 page address bits (PA7 - PA0) that specify the page in

the main memory to be erased, and eight dummy bits.

When a low-to-high transition occurs on the CS pin, the device will erase the selected page (the erased state is a Logic

1). The erase operation is internally self-timed and should take place in a maximum time of t

RDY/BUSY bit in the Status Register will indicate that the device is busy.

The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. If

an erase error arises, it will be indicated by the EPE bit in the Status Register.

SCK

CS

SI

SO

MSB

MSB

23

1

0

00000010

67

5

410 11

9

812

39

37 38

33

36

35

34

31 32

29 30

OPCODE

HIGH-IMPEDANCE

AAAA

AAA

A

A

MSB

DDDDDDD

D

ADDRESS BITS A23-A0

DATA IN

SCK

CS

SI

SO

MSB

MSB

23

1

0

00000010

67

5

49

839

37 38

33

36

35

34

31 32

29 30

OPCODE

HIGH-IMPEDANCE

AA

AAA

A

MSB

DDDDDDD

D

ADDRESS BITS A23-A0

DATA IN BYTE 1

MSB

DDDDDDD

D

DATA IN BYTE n