16

AT25DF512C

DS-25DF512C–030A–4/2014

will abort the operation and the user-programmable portion of the OTP Security Register will not be programmed. The

WEL bit in the Status Register will be reset back to the logical “0” state if the OTP Security Register program cycle aborts

due to an incomplete address being sent, an incomplete byte of data being sent, the CS pin being deasserted on uneven

byte boundaries, or because the user-programmable portion of the OTP Security Register was previously programmed.

While the device is programming the OTP Security Register, the Status Register can be read and will indicate that the

device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the t

OTPP

time to determine if the data bytes have finished programming. At some point before the OTP Security Register

programming completes, the WEL bit in the Status Register will be reset back to the logical “0” state.

If the device is powered-down during the OTP Security Register program cycle, then the contents of the 64-byte user

programmable portion of the OTP Security Register cannot be guaranteed and cannot be programmed again.

The Program OTP Security Register command utilizes the internal 256-buffer for processing. Therefore, the contents of

the buffer will be altered from its previous state when this command is issued.

Figure 10-1. Program OTP Security Register

10.2

Read OTP Security Register

The OTP Security Register can be sequentially read in a similar fashion to the Read Array operation up to the maximum

clock frequency specified by f

of 77h must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in

to specify the starting address location of the first byte to read within the OTP Security Register. Following the three

address bytes, two dummy bytes must be clocked into the device before data can be output.

After the three address bytes and the dummy bytes have been clocked in, additional clock cycles will result in OTP

Security Register data being output on the SO pin. When the last byte (00007Fh) of the OTP Security Register has been

read, the device will continue reading back at the beginning of the register (000000h). No delays will be incurred when

wrapping around from the end of the register to the beginning of the register.

Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can

be deasserted at any time and does not require that a full byte of data be read.

SCK

CS

SI

SO

MSB

MSB

23

1

0

10011011

67

5

49

839

37 38

33

36

35

34

31 32

29 30

OPCODE

HIGH-IMPEDANCE

AA

AAA

A

MSB

DDDDDDD

D

ADDRESS BITS A23-A0

DATA IN BYTE 1

MSB

DDDDDDD

D

DATA IN BYTE n