ADAV802_15 datasheet(18/53 Pages) AD

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ADAV802

Preliminary Technical Data

Rev. Pr G | Page 18 of 53

is 16 samples. However, the Group Delay and Mute In register

can be used to increase this offset. The number of input samples

added to the write pointer of the FIFO on the SRC is 16 + Bits

6-0 of the Group Delay register. This feature is useful in vari-

speed applications in order to prevent the read pointer to the

FIFO running ahead of the write pointer. When set, bit 7 of the

Group Delay and Mute In register will soft mute the sample

rate. Increasing the offset of the write address pointer is useful

for applications when small changes in the sample rate ratio

between fS_IN and fS_OUT are expected. The maximum decimation

rate can be calculated from the RAM word depth and the group

delay as (512−16)/64 taps = 7.75 for short group delay and (512-

64)/64 taps = 7 for long group delay.

The digital servo loop is essentially a ramp filter that provides

the initial pointer to the address in RAM and ROM for the start

of the FIR convolution. The RAM pointer is the integer output

of the ramp filter while the ROM is the fractional part. The

digital servo loop must be able to provide excellent rejection of

jitter on the fS_IN and fS_OUT clocks as well as measure the arrival

of the fS_OUT clock within 4.97 ps. The digital servo loop will also

divide the fractional part of the ramp output by the ratio of

fS_IN/fS_OUT for the case when fS_IN > fS_OUT, to dynamically alter

the ROM coefficients.

The digital servo loop is implemented with a multi-rate filter. To

settle the digital servo loop filter more quickly upon startup or a

change in the sample rate, a “fast mode” was added to the filter.

When the digital servo loop starts up or the sample rate is

changed, the digital servo loop kicks into “fast mode” to adjust

and settle on the new sample rate. Upon sensing the digital

servo loop settling down to some reasonable value, the digital

servo loop will kick into “normal” or “slow mode.”

During “fast mode” the MUTE_OUT bit in the Sample Rate

Error register is asserted to let the user know clicks or pops may

be present in the digital audio data. The output of the SRC can

be muted, by asserting bit 7 of the Group Delay & Mute register

until the SRC has changed to “slow mode”. The MUTE_OUT bit

can be set to generate an interrupt when the SRC changes to

“slow mode” indicating that the data will be sample rate

converted accurately. The frequency response of the digital

servo loop for "fast mode" and "slow mode" are shown in Figure

14. The FIR filter is a 64-tap filter in the case of fS_OUT ≥ fS_IN and

is (fS_IN/fS_OUT) × 64 taps for the case when fS_IN > fS_OUT. The FIR

filter performs its convolution by loading in the starting address

of the RAM address pointer and the ROM address pointer from

the digital servo loop at the start of the fS_OUT period. The FIR

filter then steps through the RAM by decrementing its address

by 1 for each tap, and the ROM pointer increments its address

by the (fS_OUT/fS_IN) × 220 ratio for fS_IN > fS_OUT or 220 for fS_OUT ≥

fS_IN. Once the ROM address rolls over, the convolution is

completed. The convolution is performed for both the left and

right channels, and the multiply accumulate circuit used for the

convolution is shared between the channels. The fS_IN/fS_OUT

sample rate ratio circuit is used to dynamically alter the

coefficients in the ROM for the case when fS_IN >fS_OUT. The ratio

is calculated by comparing the output of an fS_OUT counter to the

output of an fS_IN counter. If fS_OUT >fS_IN, the ratio is held at one.

If fS_IN > fS_OUT, the sample rate ratio is updated if it is different

by more than two fS_OUT periods from the previous fS_OUT to fS_IN

comparison. This is done to provide some hysteresis to prevent

the filter length from oscillating and causing distortion.

REG: 0x00

BITS 1-0

REG: 0x76

BIT 0

REG: 0x76

BIT 1

SRC

MCLK

AUXILIARY IN

PLAYBACK

DIR

ADC

REG: 0x62

BITS 7-6

SRC

INPUT

SRC

OUTPUT

Figure 13. Clock and Data Path Control on the SRC

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

-200

-210

-220

0.01

0.1

100

1e3

1e4

1e5

FREQUENCY - Hz

SLOW MODE

FAST MODE

Figure 14. Frequency Response of the Digital Servo Loop. fS_IN is the X-Axis,

fS_OUT = 192 KHz, Master Clock is 30 MHz

PLL SECTION

The ADAV802 features a dual PLL configuration to generate

independent system clocks for asynchronous operation. Figure

17 shows the block diagram of the PLL section. The PLL

generates the internal and system clocks from a 27MHz clock.

This clock is generated either by a crystal connected between

XIN and XOUT, as shown in Figure 15 or from an external

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