ADAV802_15 datasheet(28/53 Pages) AD

28 / 53 page

ADAV802

Preliminary Technical Data

Rev. Pr G | Page 28 of 53

Table 26. SRC & Clock Control Register

CLK2-

CLK1-

MCLK-

SRCDIV1

SRCDIV

DIV1

DIV0

DIV1

DIV0

SEL1

SEL0

ADDRESS = 0000000

SRCDIV1-0

Divides the SRC Master Clock

00 = The SRC Master Clock is not divided

01 = The SRC Master Clock is divided by 1.5

10 = The SRC Master Clock is divided by 2

11= The SRC Master Clock is divided by 3

CLK2DIV1-0

Clock Divider for Internal Clock 2 (ICLK2)

00 = Divide by 1

01 = Divide by 1.5

10 = Divide by 2

11 = Divide by 3

CLK1DIV1-0

Clock Divider for Internal Clock 1 (ICLK1)

00 = Divide by 1

01 = Divide by 1.5

10 = Divide by 2

11 = Divide by 3

MCLKSEL1-0

Clock Selection for the SRC Master Clock

00 = Internal Clock 1

01 = Internal Clock 2

10 = PLL Recovered Clock (512 × fS)

11 = PLL Recovered Clock (256 × fS)

Table 27. SPDIF Loopback Control Register

RES

TxMUX

ADDRESS = 0000011

TxMUX

Selects the source for SPDIF Output (DITOUT)

0 = SPDIF Transmitter - Normal Mode

1 = DIRIN - Loopback Mode

ADAV802 Datasheet(PDF) 28 Page - Analog Devices

ADAV802 Datasheet(HTML) 28 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

Datasheet Download

Link URL