ADE7758_15 datasheet(36/72 Pages) AD

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ADE7758

Data Sheet

Rev. E | Page 36 of 72

The phase-shift filter has –90° phase shift when the integrator is

enabled and +90° phase shift when the integrator is disabled. In

addition, the filter has a nonunity magnitude response. Because

the phase-shift filter has a large attenuation at high frequency,

the reactive power is primarily for the calculation at line

frequency. The effect of harmonics is largely ignored in the

reactive power calculation. Note that because of the magnitude

characteristic of the phase shifting filter, the LSB weight of the

reactive power calculation is slightly different from that of the

active power calculation (see the Energy Registers Scaling

section). The ADE7758 uses the line frequency of the phase

selected in the FREQSEL[1:0] bits of the MMODE[1:0] to

compensate for attenuation of the reactive energy phase shift

filter over frequency (see the Period Measurement section).

Reactive Power Gain Calibration

The average reactive power from the LPF output in each phase

can be scaled by ±50% by writing to the phase’s VAR gain register

(AVARG, BVARG, or CVARG). The VAR gain registers are twos

complement, signed registers and have a resolution of 0.024%/LSB.

The function of the VAR gain registers is expressed by

⎟

⎠

⎞

⎜

⎝

⎛ +

gister

Gain

VAR

Output

LPF

Power

Reactive

Average

(32)

The output is scaled by –50% by writing 0x800 to the VAR gain

registers and increased by +50% by writing 0x7FF to them.

These registers can be used to calibrate the reactive power (or

energy) calculation in the ADE7758 for each phase.

Reactive Power Offset Calibration

The ADE7758 incorporates a VAR offset register on each phase

(AVAROS, BVAROS, and CVAROS). These are signed twos

complement, 12-bit registers that are used to remove offsets in

the reactive power calculations. An offset can exist in the power

calculation due to crosstalk between channels on the PCB or in

the chip itself. The offset calibration allows the contents of the

reactive power register to be maintained at 0 when no reactive

power is being consumed. The offset registers’ resolution is the

same as the active power offset registers (see the Apparent

Power Offset Calibration section).

Sign of Reactive Power Calculation

Note that the average reactive power is a signed calculation. As

stated previously, the phase shift filter has –90° phase shift when

the integrator is enabled and +90° phase shift when the

integrator is disabled.

Table 12 summarizes the relationship between the phase difference

between the voltage and the current and the sign of the resulting

VAR calculation.

The ADE7758 has a sign detection circuit for the reactive power

calculation. The REVPRP bit (Bit 18) in the interrupt status

phases changes. The phases monitored are selected by TERMSEL

bits in the COMPMODE register (see Table 21). If the REVPRP

bit is set in the mask register, the IRQ logic output goes active

low (see the

section). Note that this bit is set whenever

there is a sign change; that is, the bit is set for either a positive-

to-negative change or a negative-to-positive change of the sign

bit. The response time of this bit is approximately 176 ms for a

full-scale signal, which has an average value of 0xCCCCD at the

low-pass filter output. For smaller inputs, the time is longer.

Interrupts

CLKIN

AverageVal

sponseTime

⎥

⎦

⎤

⎢

⎣

⎡

≅

(33)

Table 12. Sign of Reactive Power Calculation

Φ1

Integrator

Sign of Reactive Power

Between 0 to +90

Off

Positive

Between −90 to 0

Off

Negative

Between 0 to +90

Positive

Between −90 to 0

Negative

1 Φ is defined as the phase angle of the voltage signal minus the current

signal; that is, Φ is positive if the load is inductive and negative if the load is

capacitive.

Reactive Energy Calculation

Reactive energy is defined as the integral of reactive power.

()dt

Energy

Reactive

∫

(34)

Similar to active power, the ADE7758 achieves the integration

of the reactive power signal by continuously accumulating the

reactive power signal in the internal 41-bit accumulation

registers. The VAR-hr registers (AVARHR, BVARHR, and

CVARHR) represent the upper 16 bits of these internal

registers. This discrete time accumulation or summation is

equivalent to integration in continuous time. Equation 35

expresses the relationship

()

⎭

⎬

⎫

⎩

⎨

⎧

∑

∫

∞

→

Lim

Energy

Reactive

(35)

where:

n is the discrete time sample number.

T is the sample period.

Figure 73 shows the signal path of the reactive energy accumula-

tion. The average reactive power signal is continuously added

to the internal reactive energy register. This addition is a signed

operation. Negative energy is subtracted from the reactive energy

of the VAR divider register before it is added to the corresponding

VAR-hr accumulation registers. When the value in the

VARDIV[7:0] register is 0 or 1, the reactive power is accumulated

without any division.

VARDIV is an 8-bit unsigned register that is useful to lengthen

the time it takes before the VAR-hr accumulation registers

overflow.

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