ADE7758_15 datasheet(67/72 Pages) AD

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Data Sheet

ADE7758

Rev. E | Page 67 of 72

LINE CYCLE ACCUMULATION MODE REGISTER (0x17)

The functionalities involved the line-cycle accumulation mode in the ADE7758 are defined by writing to the LCYCMODE register.

Table 22 summarizes the functionality of each bit in the LCYCMODE register.

Table 22. LCYCMODE Register

Bit

Location

Bit

Mnemonic

Default

Value

Description

LWATT

Setting this bit places the watt-hour accumulation registers (AWATTHR, BWATTHR, and CWATTHR

registers) into line-cycle accumulation mode.

LVAR

Setting this bit places the VAR-hour accumulation registers (AVARHR, BVARHR, and CVARHR registers)

into line-cycle accumulation mode.

LVA

Setting this bit places the VA-hour accumulation registers (AVAHR, BVAHR, and CVAHR registers) into

line-cycle accumulation mode.

3 to 5

ZXSEL

These bits select the phases used for counting the number of zero crossings in the line-cycle

accumulation mode. Bit 3, Bit 4, and Bit 5 select Phase A, Phase B, and Phase C, respectively. More than

one phase can be selected for the zero-crossing detection, and the accumulation time is shortened

accordingly.

RSTREAD

Setting this bit enables the read-with-reset for all the WATTHR, VARHR, and VAHR registers for all three

phases, that is, a read to those registers resets the registers to 0 after the content of the registers have

been read. This bit should be set to Logic 0 when the LWATT, LVAR, or LVA bits are set to Logic 1.

FREQSEL

Setting this bit causes the FREQ (0x10) register to display the period, instead of the frequency of the

line input.

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