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AN4266 Datasheet(PDF) 52 Page - STMicroelectronics

Part # AN4266
Description  Safety application guide for SPC56xL70xx family
PDF  76 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN4266 Datasheet(HTML) 52 Page - STMicroelectronics

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Functional safety requirements for application software
AN4266
52/76
Doc ID 024283 Rev 2
Since power is critical to the operation of the SPC56xL70xx there is built-in redundancy to
the PMU core LVDs and HVDs. LVD_DIG_MAIN and HVD_DIG_MAIN monitor the digital
core voltage and have backups for additional safety protection (LVD_DIG_BKUP and
HVD_DIG_BKUP). Internal architecture allows for testing of the functionality of the main and
back up LVD_DIG and HVD_DIG, as well as trimming circuitries (See Figure 15). The
PMUCTRL module provides software initialized BISTs which test the digital core supply
HVD and LVD (both main and backup).
Figure 15.
Logic scheme of the LVD_DIG and HVD_DIG
If the self-test circuitry detects a fault in the main or backup detectors the reaction will be
one of the following (See “Built In Self-test (BIST)” subsection of the “Power Management
Unit (PMU)” section in the SPC56xL70xx Reference Manual):
●
Critical Fault (CF[21]) triggered and one or more of the following:
–
Main Low Voltage Detector Pending – PMUCTRL_IRQS[MLVDP] = 1
–
Backup Low Voltage Detector Pending – PMUCTRL_IRQS[BLVDP] = 1
–
Main High Voltage Detector Pending – PMUCTRL_IRQS[MHVDP] = 1
–
Backup High Voltage Detector Pending – PMUCTRL_IRQS[BHVDP] = 1
●
Destructive reset triggered
If the self-test circuitry detects a fault in the main or backup detectors the FCCU will read a
CF.
There are dedicated LVD’s in the flash memory, I/O and VREG providing additional
redundancy. This solution is different from the 1.2 V digital core supply monitoring, but still
provides the same level of safety coverage. The outputs of the first and the second LVD are
logically AND’d in such a way that a single LVD can trigger a fault, even if the other LVD is
not functioning properly (See Figure 16).
Note: This scheme represents only the logical configuration and not the actual silicon
implementation structure.
HVD_DIG_MAIN/
self-test
circuitry
reference
voltage 2
to FCCU
to MC_RGM
(destructive reset)
to MC_RGM
digital supply
(1.2V)
reference
voltage 1
LVD_DIG_MAIN
HVD_DIG_BKUP/
LVD_DIG_BKUP



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