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AN4266 Datasheet(PDF) 22 Page - STMicroelectronics |
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AN4266 Datasheet(HTML) 22 Page - STMicroelectronics |
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22 / 76 page ![]() Functional safety requirements for application software AN4266 22/76 Doc ID 024283 Rev 2 Mandatory: The user must select one channel from the eTimer_0 module and another from the eTimer_1. Note: Rationale: To avoid CCF (eTimer_0 and eTimer_1 belonging to different lakes) Mandatory: The pads shall be configured via the appropriate pad configuration registers (SIUL_PCRn). Note: Rationale: To configure pads used by this safety function 3.13.3 Read Encoder Inputs For ASIL D applications, encoder inputs used for safety purposes are assumed to be acquired redundantly as described in the following section. Read Encoder Input means any input read related to signal transitions (rise or fall). This may also include signals coming from an encoder. Double Read Encoder Inputs Hardware elements A Double Read Encoder Input is implemented using two channels that can be provided by: ● eTimer_0 ● eTimer_1 ● SIUL When both channels are provided by the timer units, the signals of one encoder must be addressed to eTimer_0 and the signals of the other encoder must be addressed to eTimer_1. Alternatively, one or both channels can be provided by the SIUL, which supports interrupt based reading of encoder signals. This means the SIUL must use general purpose inputs which have edge detection interrupts (See Figure 3 for details). Mandatory: One channel must be addressed by eTimer_0, and the other by eTimer_1. Note: Rationale: Two different eTimers must be used to avoid CCF (eTimer_0 and eTimer_1 belonging to different lakes). For each signal, the SIUL can provide additional channels to support interrupt-based reading. Mandatory: In this configuration, the SIUL must be correctly configured to forward one or two interrupt-based event readings. Note: Rationale: To configure pads used by this safety function Mandatory: The input pads must not be physically adjacent (see Section 7, I/O pin/ball configuration for details). Table 4. Software BIST and/or test Software BIST or test Frequency ETIMER0_SWTEST_REGCRC Once after programming ETIMER1_SWTEST_REGCRC Once after programming SIUL_SWTEST_REGCRC Once after programming ETIMERI_SWTEST_CMP Once for every acquisition |
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