UM1693 datasheet(7/196 Pages) STMICROELECTRONICS

7 / 196 page

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UM1693

List of figures

Figure 1.

Typical application schematics – monolithic devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2.

Typical application schematics – hybrid devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 3.

Voltage levels during reverse battery (diode + resistor protection). . . . . . . . . . . . . . . . . . . 18

Figure 4.

Negative GND shift (TDEMAG > tD_STBY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 5.

GND resistor requirements (inductive load)–test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 6.

Measurement example (tDEMAG > tD_STBY) without GND resistor . . . . . . . . . . . . . . . . . . . 22

Figure 7.

Measurement example (tDEMAG > tD_STBY) with 4.7 k

Ω GND resistor . . . . . . . . . . . . . 23

Figure 8.

Generic schematic and test setup with N-channel MOSFET in GND line . . . . . . . . . . . . . 26

Figure 9.

MOSFET solution in GND – experiment VND7020AJ-E, ISOpulse 1 (-150V, 90

Ω) . . . . . 27

Figure 10.

Reverse battery test VN7016AJ-E (13.5 V

→ -4 V, 82 mΩ, R2 = 15 kΩ) as per LV 124:

2009-10 standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 11.

Generic schematic and test setup with P-channel MOSFET in VCC line . . . . . . . . . . . . . . 29

Figure 12.

MOSFET solution in VCC – experiment VND7020AJ-E-E, ISOpulse 1 (-100 V, 90 Ω). . . . 30

Figure 13.

Reverse battery test according to LV 124:2009-10: VN7016AJ-E (13.5 V at -4 V,

82 m

Ω, R2 = 1kΩ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 14.

Reverse polarity protection – reverse FET protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 15.

Maximum current versus duration time of VN5R003H-E . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 16.

Conducted hazards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 17.

Radiated hazards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 18.

Various surges occurring in the supply rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 19.

Internal structures involved during application of ISO 7637-2 pulse 1 in a monolithic HSD

and indication of pin voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 20.

Basic test setup for ISO 7637-2 pulses applied to VND7020AJ-E . . . . . . . . . . . . . . . . . . . 40

Figure 21.

Internal structures involved during application of ISO 7637-2 (2004) pulse 1 in Hybrid

HSD and indication of pin voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 22.

Internal structures involved during application of ISO 7637-2 (2011) pulse 1 in Hybrid

HSD and indication of pin voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 23.

Basic test setup for ISO 7637-2 (2004) pulses applied to VN7004AH-E . . . . . . . . . . . . . . 44

Figure 24.

Recommended GND network for ISO 7637-2 (2011) level IV . . . . . . . . . . . . . . . . . . . . . . 45

Figure 25.

Basic Test setup for ISO 7637-2 (2011) pulses applied to VN7004AH-E. . . . . . . . . . . . . . 46

Figure 26.

Latch functionality - behavior in hard short circuit condition (Tjunction << TTSD). . . . . . . . .50

Figure 27.

Latch functionality - behavior in hard short circuit condition (TR < Tjunction < TTSD) . . . . 50

Figure 28.

Latch functionality - behavior in hard short circuit condition (autorestart mode and

latch-off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 29.

Standby mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Figure 30.

Standby state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 31.

FR handling example - bulb inrush blanking (VNQ7140AJ-E) . . . . . . . . . . . . . . . . . . . . . . 53

Figure 32.

Common FaultRST pin handling example – basic schematic (without decoupling

components) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 33.

FaultRST pin handling concept. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 34.

FaultRST pin handling example - overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 35.

FaultRST pin handling example – detail of diagnostic period . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 36.

FaultRST pin handling example – detail of unlatch pulse (Ch. 2) . . . . . . . . . . . . . . . . . . . . 56

Figure 37.

Monolithic devices, common power supply rails, separate MultiSense . . . . . . . . . . . . . . . 60

Figure 38.

Monolithic devices, common power supply rails, common MultiSense . . . . . . . . . . . . . . . 61

Figure 39.

Monolithic devices, separate power supply rails, common MultiSense . . . . . . . . . . . . . . . 62

Figure 40.

Monolithic and hybrid device, separate power supply rails, separate MultiSense . . . . . . . 63

Figure 41.

Hybrid devices, separate power supply rails, common MultiSense . . . . . . . . . . . . . . . . . . 64

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