AN2836 datasheet(11/57 Pages) STMICROELECTRONICS

11 / 57 page

AN2836

Designing an application with L6225, L6226, L6227

Doc ID 15084 Rev 1

11/57

inductance of the PCB path from the pin to GND. This spike is followed by a stable negative

voltage due to the drop on RSENSE. One of the two OUT pins of the bridge sees a similar

behavior, but with a slightly larger voltage due to the forward recovery time of the integrated

freewheeling diode and the forward voltage drop across it (see Figure 5). Typical duration of

this spike is 30 ns. At the same time, the other OUT pin of the same bridge sees a voltage

above VS, due to the PCB inductance and voltage drop across the high-side (integrated)

freewheeling diode, as the current reverses direction and flows into the bulk capacitor. It

turns out that the highest differential voltage can be observed between the two OUT pins of

the same bridge, during the deadtime at a phase change, and this must always be kept

below 60 V [3].

Figure 5.

Currents and voltages during the deadtime at a phase change

Figure 6 shows the voltage waveforms at the two OUT pins referring to an application, with a

peak output current of 1.4 A, VS = 52 V, RSENSE = 0.33 Ω, TJ = 25 °C (approximately) and a

good PCB layout. Below ground spike amplitude is –2.65 V for one output, the other OUT

pin is at about 57 V. In these conditions, total differential voltage reaches almost 60 V, which

is the absolute maximum rating for the DMOS. Keeping differential voltage between two

output pins belonging to the same full bridge within rated values is a must that can be

accomplished with proper selection of bulk capacitor value and equivalent series resistance

(ESR), according to current peaks and chopping style and adopting good layout practices to

minimize PCB parasitic inductances (see below) [3].

Figure 6.

Voltage at the two outputs during the deadtime at a phase change

AN2836 Datasheet(PDF) 11 Page - STMicroelectronics