AN3393 datasheet(91/103 Pages) STMICROELECTRONICS

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AN3393

First-in first-out (FIFO) buffer

103

The trigger used to activate Stream-to-FIFO, Bypass-to-Stream and Bypass-to-FIFO modes

is related to the INT_SM2 bit value of the STAT register and does not depend on the

interrupt pin value and polarity. The trigger is generated also if the selected interrupt is not

driven to an interrupt pin.

The WTMP[4:0] bits define the watermark level.

10.2.3

FIFO source register (2Fh)

This register is updated at every ODR and provides information about the FIFO buffer

status.



WTM bit is set high when the value of the FSS[4:0] bits exceeds the watermark level in

the WTMP[4:0] bits of the FIFO_CTRL register. The WTM bit is reset when FIFO data

are read and the content of the FSS bits in the FIFO_SRC register becomes lower than

the watermark level (WTMP bits in FIFO_CTRL register).



OVRN bit is set high when the FIFO buffer is full; this means that the FIFO buffer

contains 32 unread samples. At the following ODR a new sample set replaces the

oldest FIFO value.



EMPTY flag is set high when all FIFO samples have been read and FIFO is empty.



FSS[4:0] values provide information about the number of samples in the FIFO, as

shown in Table 101. When FIFO is enabled, this value increases at the ODR frequency

until the buffer is full, whereas, it decreases every time that one sample set is retrieved

from FIFO. When the EMPTY bit is “0”, FSS[4:0] is the number of samples in the

FIFO - 1. When the EMPTY bit is “1”, FSS[4:0] has no meaning and is always equal to

“0”.

Table 100. FIFO_SRC_REG

WTM

OVRN

EMPTY

FSS4

FSS3

FSS2

FSS1

FSS0

Table 101. FIFO_SRC_REG behavior assuming WTMP[4:0] = 15

WTM

OVRN

Empty

FSS[4:0]

FIFO samples

Timing

00000

t0 + 1/ODR

00001

t0 + 2/ODR

...

01110

t0 + 15/ODR

01111

t0 + 16/ODR

10000

t0 + 17/ODR

...

11110

t0 + 31ODR

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