AN3393 datasheet(16/103 Pages) STMICROELECTRONICS

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Interrupt generation

AN3393

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DocID018750 Rev 4

Interrupt generation

The LIS3DSH can be configured to generate interrupt signals activated by user-defined

motion patterns. To do this, pins 9 and 11 are used respectively as INT2 and INT1.

Interrupt signals are the main results of the two state machines; they are triggered when

output/stop/continue states are reached in one of the two state machines. When an interrupt

occurs, the INT_SM1 or the INT_SM2 bit on the STAT register (18h) is updated.

Both State Machine 1 and State Machine 2 can be routed to INT1 and INT2, by setting the

SM1_PIN and SM2_PIN bits in the CTRL_REG1 and CTRL_REG2 registers.

Moreover, the device may be configured to have a HW signal to determine when a new set

of measurement data is available for reading. By setting the DR_EN bit to ‘1’ in the

CTRL_REG3 register (23h), the data-ready signal is routed to INT1 and the DRDY bit in the

STAT register (18h) is updated according to the status.

Interrupt signal polarity is set through the IEA bit while the signal shape (latched/pulsed) is

set through the IEL bit in the CTRL_REG3 register (23h). When the interrupt is pulsed, it has

a fixed duration of 50 μs.

An interrupt on the INT1 pin can also be generated when a FIFO buffer is used, such as for

a programmable watermark level, FIFO empty or FIFO full events (see CTRL_REG6

Finally, interrupts can be enabled/disabled by setting bits INT2_EN and INT1_EN in the

CTRL_REG3 register (23h).

Table 5 indicates all the interrupt bits in the LIS3DSH.

Figure 2 shows how the interrupt signals can be routed to the interrupt pins.

Table 5. Interrupt bits

Bit

Behavior

INT_SM1

STAT (18h)

Updated when INT1 occurs

INT_SM2

STAT (18h)

Updated when INT2 occurs

SM1_PIN

CTRL_REG1 (21h)

State Machine 1 interrupt routed to INT1/INT2

SM2_PIN

CTRL_REG2 (22h)

State Machine 2 interrupt routed to INT1/INT2

DR_EN

CTRL_REG3 (23h)

Enable/disable data-ready signal (routed to INT1)

IEA

CTRL_REG3 (23h)

Define interrupt signal polarity (active low / active high)

IEL

CTRL_REG3 (23h)

Define interrupt signal shape: latched / pulsed

P1_EMPTY

CTRL_REG6 (25h)

Enable FIFO empty indication on INT1 pin

P1_WTM

CTRL_REG6 (25h)

Enable FIFO watermark interrupt on INT1 pin

P1_OVERRUN

CTRL_REG6 (25h)

Enable FIFO overrun interrupt on INT1 pin

P2_BOOT

CTRL_REG6 (25h)

Enable BOOT interrupt on INT2 pin

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