AN2834 datasheet(16/45 Pages) STMICROELECTRONICS

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ADC errors

AN2834

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DocID15067 Rev 2

2.2.3

External reference voltage parameters

In case of usage external source for reference voltage (on VREF+ pin) there are important

parameters of this external reference source. It is important to look at three reference

voltage specifications: temperature drift, voltage noise, long term stability.

2.2.4

Analog input signal noise

Small but high-frequency signal variation can result in big conversion errors during sampling

time. This noise is generated by electrical devices, for example, motors, engine ignition,

power lines, and so on, and affects the source signal (for example a sensor) by adding an

unwanted signal. As a consequence, the conversion results of the ADC are not accurate.

2.2.5

ADC dynamic range bad match for maximum input signal amplitude

It is very important that the ADC dynamic range matches the maximum amplitude of the

signal to be converted to have the maximum ADC conversion precision. Let us assume that

the signal to be converted varies between 0 V to 2.5 V and that VREF+ is equal to 3.3 V. The

maximum signal value converted by the ADC is 3102 (2.5 V) as shown in Figure 14. In this

case, there are 993 unused transitions (4095 – 3102 = 993). This implies a loss in the

converted signal accuracy.

See Section 3.2.5: Matching the ADC dynamic range to the maximum signal amplitude on

page 23 for details on how to have the ADC dynamic range matching the maximum input

signal amplitude.

Figure 14. Input signal amplitude vs. ADC dynamic range

2.2.6

Effect of the analog signal source resistance

The impedance of the analog signal source, or series resistance (RAIN), between the source

and pin causes a voltage drop across it because of the current flowing into the pin. The

charging of the internal sampling capacitor CADC is controlled by switches with resistance

RADC.

With the addition of source resistance (with RADC), the time required to fully charge the hold

capacitor increases. Figure 15 shows the analog signal source resistance effect.

The effective charging of CADC is governed by RADC + RAIN, so the charging time constant

becomes tc = (RADC+RAIN) × CADC. If the sampling time is less than the time required to fully

charge the CADC through RADC + RAIN (ts < tc), the digital value converted by the ADC is

less than the actual value.

2.5 V

(3102h)

VREF+ = 3.3 V

(4095h)

unused ADC transition range

ai15499

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