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UM0851 Datasheet(PDF) 61 Page - STMicroelectronics |
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UM0851 Datasheet(HTML) 61 Page - STMicroelectronics |
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61 / 245 page ![]() UM0851 Communication device drivers Doc ID 16604 Rev 2 61/245 4.3 USB Host 4.3.1 Hardware overview Within its high-speed (HS) connection subsystem, SPEAr provides Synopsys's USB 2.0 Host fully compliant with the universal serial bus specification (version 2.0), and offering an interface to the industry-standard AHB bus. The high speed connection subsystem in SPEAr provides in the following numbers/features of USB host controllers for SPEAr 600/300. The main features provided by each USB 2.0 Host are listed below: ● PHY interface implementing a USB 2.0 transceiver macro cell interface (UTMI) fully compliant with UTMI specification (revision 1.05), to execute serialization and de- serialization of transmissions over the USB line. ● 30 MHz clock for 16-bit interface, supported by the UTMI PHY interface. ● USB 2.0 Host controller (UHC) connected to the AHB bus that generates the commands for the UTMI PHY. ● The UHC complies with both the enhanced host controller interface (EHCI) specification (version 1.0) and the open host controller interface (OHCI) specification (version 1.0a). ● All clock synchronization is handled within the UHC. ● An AHB slave for each controller (EHCI and OHCI), acting as a programming interface for access to control and status registers. ● An AHB master for each controller (EHCI and OHCI) for data transfer to system memory, supporting 8, 16, and 32-bit wide data transactions on the AHB bus. Table 19. USB host configuration in SPEAr SPEAr600 SPEAr300 Two USB hosts compatible with USB 2.0 high- speed specification. They can work simultaneously either in full-speed or in high- speed mode. One USB host controller compatible with USB 2.0 high-speed specification managing two ports. The peripherals have dedicated channels to the multi-port memory controller and four slave ports for CPU programming. The peripheral has dedicated channel to the multi-port memory controller and two slave ports for CPU programming. The UHC supports the 480 Mbps high-speed (HS) for USB 2.0 through an embedded EHCI host controller, as well as the 12 Mbps full-speed (FS) and the 1.5 Mbps low-speed (LS) for USB 1.1 through one integrated OHCI host controller. The UHC supports the 480 Mbps high-speed (HS) for USB 2.0 through an embedded EHCI host controller, as well as the 12 Mbps full-speed (FS) and the 1.5 Mbps low-speed (LS) for USB 1.1 through two integrated OHCI Host controllers. |
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