AN4488 datasheet(8/44 Pages) STMICROELECTRONICS

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Power supplies

AN4488

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DocID026304 Rev 3

2.1.3

Voltage regulator

The voltage regulator is always enabled after reset. It works in three different modes

depending on the application modes.

•

in Run mode, the regulator supplies full power to the 1.2 V domain (core, memories

and digital peripherals)

•

in Stop mode, the regulator supplies low power to the 1.2 V domain, preserving the

contents of the registers and SRAM

•

in Standby mode, the regulator is powered down. The contents of the registers and

SRAM are lost except for those concerned with the Standby circuitry and the Backup

domain.

Note:

Depending on the selected package, there are specific pins that should be connected either

to VSS or VDD to activate or deactivate the voltage regulator. Refer to section “Voltage

regulator “ in datasheet for details.

2.2

Power supply schemes

The circuit is powered by a stabilized power supply, VDD.

Caution:

The VDD voltage range is 1.8 V to 3.6 V (down to 1.7 V with some restrictions, see relative

DataSheets for details)

•

The VDD pins must be connected to VDD with external decoupling capacitors: one

single Tantalum or Ceramic capacitor (min. 4.7 µF typ.10 µF) for the package + one

100 nF Ceramic capacitor for each VDD pin.

•

The VBAT pin can be connected to the external battery (1.65 V < VBAT < 3.6 V). If no

external battery is used, it is recommended to connect this pin to VDD with a 100 nF

external ceramic decoupling capacitor.

•

The VDDA pin must be connected to two external decoupling capacitors (100 nF

Ceramic + 1 µF Tantalum or Ceramic).

•

The VREF+ pin can be connected to the VDDA external power supply. If a separate,

external reference voltage is applied on VREF+, a 100 nF and a 1 µF capacitors must

be connected on this pin. In all cases, VREF+ must be kept between (VDDA-1.2 V) and

VDDA with minimum of 1.7 V.

•

must be kept between 1.65 V and VDDA.

•

Additional precautions can be taken to filter analog noise:

–VDDA can be connected to VDD through a ferrite bead.

–The VREF+ pin can be connected to VDDA through a resistor (typ. 47 Ω).

•

For the voltage regulator configuration, there is specific BYPASS_REG pin (not

available on all packages) that should be connected either to VSS or VDD to activate or

deactivate the voltage regulator specific.

–

Refer to Section 2.3.6 and section "Voltage regulator" of the related device

datasheet for details.

•

When the voltage regulator is enabled, VCAP1 and VCAP2 pins must be connected to

2*2.2 µF LowESR < 2

Ω Ceramic capacitor (or 1*4.7 µF LowESR < 1Ω Ceramic

capacitor if only VCAP1 pin is provided on some packages).

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