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AN4488

Debug management

6.3.2

Flexible SWJ-DP pin assignment

After reset (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned as

dedicated pins immediately usable by the debugger host (note that the trace outputs are not

assigned except if explicitly programmed by the debugger host).

However, some of the JTAG pins shown in Table 9 can be configured to an alternate

function through the GPIOx_AFRx registers.

Table 9 shows the different possibilities to release some pins.

For more details, see the reference manual (Table 1), available from the STMicroelectronics

website www.st.com.

6.3.3

Internal pull-up and pull-down resistors on JTAG pins

The JTAG input pins must not be floating since they are directly connected to flip-flops to

control the debug mode features. Special care must be taken with the SWCLK/TCK pin that

is directly connected to the clock of some of these flip-flops.

Table 8. Debug port pin assignment

SWJ-DP pin name

JTAG debug port

SW debug port

assignmen

Type

Description

Type

Debug assignment

JTMS/SWDIO

JTAG test mode

selection

I/O

Serial wire data

input/output

PA13

JTCK/SWCLK

JTAG test clock

Serial wire clock

PA14

JTDI

JTAG test data input

PA15

JTDO/TRACESWO

JTAG test data output

TRACESWO if async

trace is enabled

PB3

JNTRST

JTAG test nReset

PB4

Table 9. SWJ I/O pin availability

Available Debug ports

SWJ I/O pin assigned

PA13 /

JTMS/

SWDIO

PA14 /

JTCK/

SWCLK

PA15 /

JTDI

PB3 /

JTDO

PB4/

JNTRST

Full SWJ (JTAG-DP + SW-DP) - reset state

Full SWJ (JTAG-DP + SW-DP) but without

JNTRST

JTAG-DP disabled and SW-DP enabled

JTAG-DP disabled and SW-DP disabled

Released

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