AN4488 datasheet(35/44 Pages) STMICROELECTRONICS

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AN4488

Recommendations

7.1

Printed circuit board

For technical reasons, it is best to use a multilayer printed circuit board (PCB) with a

separate layer dedicated to ground (VSS) and another dedicated to the VDD supply. This

provides good decoupling and a good shielding effect. For many applications, economical

reasons prohibit the use of this type of board. In this case, the major requirement is to

ensure a good structure for ground and for the power supply.

7.2

Component position

A preliminary layout of the PCB must separate the different circuits according to their EMI

contribution in order to reduce cross-coupling on the PCB, that is noisy, high-current circuits,

low-voltage circuits, and digital components.

7.3

Ground and power supply (VSS, VDD)

Every block (noisy, low-level sensitive, digital, etc.) should be grounded individually and all

ground returns should be to a single point. Loops must be avoided or have a minimum area.

The power supply should be implemented close to the ground line to minimize the area of

the supply loop. This is due to the fact that the supply loop acts as an antenna, and is

therefore the main transmitter and receiver of EMI. All component-free PCB areas must be

filled with additional grounding to create a kind of shielding (especially when using single-

layer PCBs).

7.4

Decoupling

All power supply and ground pins must be properly connected to the power supplies. These

connections, including pads, tracks and vias should have as low impedance as possible.

This is typically achieved with thick track widths and, preferably, the use of dedicated power

supply planes in multilayer PCBs.

In addition, each power supply pair should be decoupled with filtering Ceramic capacitors

(100 nF) and one single Tantalum or Ceramic capacitor (min. 4.7 µF typ.10 µF) connected

in parallel. These capacitors need to be placed as close as possible to, or below, the

appropriate pins on the underside of the PCB. Typical values are 10 nF to 100 nF, but exact

values depend on the application needs. Figure 25 shows the typical layout of such a

VDD/VSS pair.

AN4488 Datasheet(PDF) 35 Page - STMicroelectronics