AN4488 datasheet(10/44 Pages) STMICROELECTRONICS

10 / 44 page

Power supplies

AN4488

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DocID026304 Rev 3

2.3

Reset & power supply supervisor

2.3.1

Power on reset (POR) / power down reset (PDR)

The device has an integrated POR/PDR circuitry that allows proper operation starting from

1.8 V.

The device remains in the Reset mode as long as VDD is below a specified threshold,

VPOR/PDR, without the need for an external reset circuit. For more details concerning the

power on/power down reset threshold, refer to the electrical characteristics in the product

datasheets.

Figure 2. Power-on reset/power-down reset waveform

1. tRSTTEMPO is approximately 2.6 ms. VPOR/PDR rising edge is 1.74 V (typ.) and VPOR/PDR falling edge is

1.70 V (typ.). Refer to STM32F4xxxx datasheets for actual value.

The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled through

the PDR_ON pin. An external power supply supervisor should monitor VDD and should

maintain the device in reset mode as long as VDD is below a specified threshold. PDR_ON

should be connected to this external power supply supervisor. See Section 2.3.4 and

Section 2.3.5 for details.

2.3.2

Programmable voltage detector (PVD)

You can use the PVD to monitor the VDD power supply by comparing it to a threshold

selected by the PLS[2:0] bits in the Power control register (PWR_CR).

The PVD is enabled by setting the PVDE bit.

A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate

whether VDD is higher or lower than the PVD threshold. This event is internally connected to

EXTI Line16 and can generate an interrupt if enabled through the EXTI registers. The PVD

output interrupt can be generated when VDD drops below the PVD threshold and/or when

VDD rises above the PVD threshold depending on the EXTI Line16 rising/falling edge

configuration. As an example the service routine can perform emergency shutdown tasks.

AN4488 Datasheet(PDF) 10 Page - STMicroelectronics